Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0401
714/771 RM0401 Rev 3
The audio sampling frequency may be 192 KHz, 96 kHz, 48 kHz, 44.1 kHz, 32 kHz,
22.05 kHz, 16 kHz, 11.025 kHz or 8 kHz (or any other value within this range). In order to
reach the desired frequency, the linear divider needs to be programmed according to the
formulas below:
When the master clock is generated (MCKOE in the SPIx_I2SPR register is set):
f
S
= I2SxCLK / [(16*2)*((2*I2SDIV)+ODD)*8)] when the channel frame is 16-bit wide
f
S
= I2SxCLK / [(32*2)*((2*I2SDIV)+ODD)*4)] when the channel frame is 32-bit wide
When the master clock is disabled (MCKOE bit cleared):
f
S
= I2SxCLK / [(16*2)*((2*I2SDIV)+ODD))] when the channel frame is 16-bit wide
f
S
= I2SxCLK / [(32*2)*((2*I2SDIV)+ODD))] when the channel frame is 32-bit wide
Table 126 provides example precision values for different clock configurations.
Note: Other configurations are possible that allow optimum clock precision.
Table 126. Audio-frequency precision using standard 8 MHz HSE
(1)
SYSCLK
(MHz)
Data
length
I2SDIV I2SODD MCLK
Target f
S
(Hz)
Real f
S
(KHz) Error
48 16 8 0 No 96000 93750 2.3438%
48 32 4 0 No 96000 93750 2.3438%
48 16 15 1 No 48000 48387.0968 0.8065%
48 32 8 0 No 48000 46875 2.3438%
48 16 17 0 No 44100 44117.647 0.0400%
48 32 8 1 No 44100 44117.647 0.0400%
48 16 23 1 No 32000 31914.8936 0.2660%
48 32 11 1 No 32000 32608.696 1.9022%
48 16 34 0 No 22050 22058.8235 0.0400%
48 32 17 0 No 22050 22058.8235 0.0400%
48 16 47 0 No 16000 15957.4468 0.2660%
48 32 23 1 No 16000 15957.447 0.2660%
48 16 68 0 No 11025 11029.4118 0.0400%
48 32 34 0 No 11025 11029.412 0.0400%
48 16 94 0 No 8000 7978.7234 0.2660%
48 32 47 0 No 8000 7978.7234 0.2660%
48 16 2 0 Yes 48000 46875 2.3430%
48 32 2 0 Yes 48000 46875 2.3430%
48 16 2 0 Yes 44100 46875 6.2925%
48 32 2 0 Yes 44100 46875 6.2925%
48 16 3 0 Yes 32000 31250 2.3438%
48 32 3 0 Yes 32000 31250 2.3438%
48 16 4 1 Yes 22050 20833.333 5.5178%
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