Power controller (PWR) RM0401
88/771 RM0401 Rev 3
4.4.2 PWR power control/status register (PWR_CSR)
Address offset: 0x04
Reset value: 0x0000 0000 (not reset by wakeup from Standby mode)
Additional APB cycles are needed to read this register versus a standard APB read.
Bit 2 CWUF: Clear wakeup flag
This bit is always read as 0.
0: No effect.
1: Clear the WUF Wakeup Flag after 2 System clock cycles.
Bit 1 PDDS: Power-down deepsleep
This bit is set and cleared by software. It works together with the LPDS bit.
0: Enter Stop mode when the CPU enters deepsleep. The regulator status depends on the
LPDS bit.
1: Enter Standby mode when the CPU enters deepsleep.
Bit 0 LPDS: Low-power deepsleep
This bit is set and cleared by software. It works together with the PDDS bit.
0: Voltage regulator on during Stop mode.
1: Low-power Voltage regulator on during Stop mode.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res.
VOS
RDY
Res. Res. Res. Res. BRE
EWUP
1
EWUP
2
EWUP
3
Res. Res. BRR PVDO SBF WUF
r rwrwrwrw r r r r
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 VOSRDY: Regulator voltage scaling output selection ready bit
0: Not ready
1: Ready
Bits 13:10 Reserved, must be kept at reset value.
Bit 9 BRE: Backup regulator enable
When set, the Backup regulator (used to maintain the backup domain content) is enabled. If
BRE is reset, the backup regulator is switched off. Once set, the application must wait that
the Backup Regulator Ready flag (BRR) is set to indicate that the data written into the
backup registers will be maintained in the Standby and V
BAT
modes.
0: Backup regulator disabled
1: Backup regulator enabled
Note: This bit is not reset when the device wakes up from Standby mode, by a system reset,
or by a power reset.
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