Reset and clock control (RCC) RM0401
132/771 RM0401 Rev 3
5.3.18 RCC dedicated Clocks Configuration Register 2 (RCC_DCKCFGR2)
Address offset: 0x94
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1SEL Res. Res. Res. Res. Res. Res. I2C4SEL Res. Res. Res. Res. Res. Res.
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Bits 31:30 LPTIMSEL: LPTIM1 kernel clock source selection
Set and reset by software to select the LPTIM1 clock source.
00: LPTIM1 clock = APB clock
01: LPTIM1 clock = HSI clock
10: LPTIM1 clock = LSI clock
11: LPTIM1 clock = LSE clock
Bits 29:24 Reserved, must be kept at reset value.
Bits 23:22 I2C4SEL: I2C4 kernel clock source selection
Set and reset by software to select the I2C4 clock source.
00 and 11: I2C4 clock = APB clock
01: I2C4 clock = system clock
10: I2C4 clock = HSI clock
Bits 21: 0 Reserved, must be kept at reset value.