Direct memory access controller (DMA) RM0401
176/771 RM0401 Rev 3
Figure 28. FIFO structure
FIFO threshold and burst configuration
Caution is required when choosing the FIFO threshold (bits FTH[1:0] of the DMA_SxFCR
register) and the size of the memory burst (MBURST[1:0] of the DMA_SxCR register): The
content pointed by the FIFO threshold must exactly match an integer number of memory
burst transfers. If this is not in the case, a FIFO error (flag FEIFx of the DMA_HISR or
DMA_LISR register) is generated when the stream is enabled, then the stream is
automatically disabled. The allowed and forbidden configurations are described in Table 35.
The forbidden configurations are highlighted in gray in the table.
3OURCEBYTE
WORDS
BYTELANE
BYTELANE
BYTELANE
BYTELANE
&ULL%MPTY
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
$ESTINATIONWORD
3OURCEBYTE
$ESTINATIONHALFWORD
WORDS
BYTELANE
BYTELANE
BYTELANE
BYTELANE
&ULL%MPTY
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
7777
(
(
(
(
(
(
(
(
3OURCEHALFWORD
$ESTINATIONWORD
WORDS
BYTELANE
BYTELANE
BYTELANE
BYTELANE
&ULL%MPTY
(
7777
(
(
(
(
(
(
(
""""""""""""""""
""""""""""""""""
((((((((
((((((((
7777
7777
3OURCEHALFWORD
WORDS
BYTELANE
BYTELANE
BYTELANE
BYTELANE
&ULL%MPTY
$ESTINATIONBYTE
((((((((
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
(
(
(
(
(
(
(
(
""""""""
""""""""
AI
Table 35. FIFO threshold configurations
MSIZE FIFO level MBURST = INCR4 MBURST = INCR8 MBURST = INCR16
Byte
1/4 1 burst of 4 beats
Forbidden
Forbidden1/2 2 bursts of 4 beats 1 burst of 8 beats
3/4 3 bursts of 4 beats
Forbidden
Full 4 bursts of 4 beats 2 bursts of 8 beats 1 burst of 16 beats
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