RM0401 Rev 3 525/771
RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface
591
The following additional features are also available depending on the product
implementation (see Section 22.3: FMPI2C implementation):
• SMBus specification rev 3.0 compatibility:
– Hardware PEC (Packet Error Checking) generation and verification with ACK
control
– Command and data acknowledge control
– Address resolution protocol (ARP) support
– Host and Device support
– SMBus alert
– Timeouts and idle condition detection
• PMBus rev 1.3 standard compatibility
• Independent clock: a choice of independent clock sources allowing the FMPI2C
communication speed to be independent from the PCLK reprogramming
22.3 FMPI2C implementation
This manual describes the full set of features implemented in FMPI2C1
22.4 FMPI2C functional description
In addition to receiving and transmitting data, this interface converts it from serial to parallel
format and vice versa. The interrupts are enabled or disabled by software. The interface is
connected to the I
2
C bus by a data pin (SDA) and by a clock pin (SCL). It can be connected
with a standard (up to 100 kHz), Fast-mode (up to 400 kHz) or Fast-mode Plus (up to
1MHz) I
2
C bus.
This interface can also be connected to a SMBus with the data pin (SDA) and clock pin
(SCL).
If SMBus feature is supported: the additional optional SMBus Alert pin (SMBA) is also
available.
Table 84. STM32F410 FMPI2C implementation
I2C features
(1)
1. X = supported.
I2C4
7-bit addressing mode X
10-bit addressing mode X
Standard-mode (up to 100 kbit/s) X
Fast-mode (up to 400 kbit/s) X
Fast-mode Plus
(2)
(up to 1 Mbit/s)
2. 20 mA output drive for Fm+ mode is not supported.
X
Independent clock X
Wakeup from Stop mode -
SMBus/PMBus X
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