To Next Page

To Previous Page

Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401

530/771 RM0401 Rev 3

FMPI2C timings

The timings must be configured in order to guarantee a correct data hold and setup time,

used in master and slave modes. This is done by programming the PRESC[3:0],

SCLDEL[3:0] and SDADEL[3:0] bits in the FMPI2C_TIMINGR register.

The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C

configuration window

Figure 179. Setup and hold timings

06Y9

6<1&

6&/IDOOLQJHGJHLQWHUQDO

GHWHFWLRQ

6'$'(/6&/VWUHWFKHGORZE\WKH,&

6'$RXWSXWGHOD\

6&/

6'$

d,K>d/D

+''$7

6&/'(/

6&/VWUHWFKHGORZE\WKH,&

6&/

6'$

d^dhWd/D

6867$

'DWDKROGWLPHLQFDVHRIWUDQVPLVVLRQWKHGDWDLVVHQWRQ6'$RXWSXWDIWHU

WKH6'$'(/GHOD\LILWLVDOUHDG\DYDLODEOHLQ,&B7;'5

'DWDVHWXSWLPHLQFDVHRIWUDQVPLVVLRQWKH6&/'(/FRXQWHUVWDUWV

ZKHQWKHGDWDLVVHQWRQ6'$RXWSXW

069