Debug support (DBG) RM0401
744/771 RM0401 Rev 3
IDCODE read or CTRL/STAT read or ABORT write which are accepted even if the write
buffer is full.
• Because of the asynchronous clock domains SWCLK and HCLK, two extra SWCLK
cycles are needed after a write transaction (after the parity bit) to make the write
effective internally. These cycles should be applied while driving the line low (IDLE
state)
This is particularly important when writing the CTRL/STAT for a power-up request. If the
next transaction (requiring a power-up) occurs immediately, it will fail.
26.8.5 SW-DP registers
Access to these registers are initiated when APnDP=0
Table 136. SW-DP registers
A[3:2] R/W
CTRLSEL bit
of SELECT
register
Register Notes
00 Read - IDCODE
The manufacturer code is not set to ST
code. 0x2BA01477 (identifies the SW-DP)
00 Write - ABORT -
01 Read/Write 0
DP-
CTRL/STAT
Purpose is to:
– request a system or debug power-up
– configure the transfer operation for AP
accesses
– control the pushed compare and pushed
verify operations.
– read some status flags (overrun, power-
up acknowledges)
01 Read/Write 1
WIRE
CONTROL
Purpose is to configure the physical serial
port protocol (like the duration of the
turnaround time)
10 Read
READ
RESEND
Enables recovery of the read data from a
corrupted debugger transfer, without
repeating the original AP transfer.
10 Write SELECT
The purpose is to select the current access
port and the active 4-words register window
11 Read/Write
READ
BUFFER
This read buffer is useful because AP
accesses are posted (the result of a read AP
request is available on the next AP
transaction).
This read buffer captures data from the AP,
presented as the result of a previous read,
without initiating a new transaction
To Next Page
Loading...
Need help?
General
