ST STM32F410 User Manual (English)

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General-purpose timers (TIM9 and TIM11) RM0401

422/771 RM0401 Rev 3

Note: The states of the external I/O pins connected to the standard OCx channels depend on the

state of the OCx channel and on the GPIO registers.

16.4.8 TIM9 counter (TIMx_CNT)

Address offset: 0x24

Reset value: 0x0000 0000

16.4.9 TIM9 prescaler (TIMx_PSC)

Address offset: 0x28

Reset value: 0x0000

16.4.10 TIM9 auto-reload register (TIMx_ARR)

Address offset: 0x2C

Reset value: 0x0000

Table 66. Output control bit for standard OCx channels

CCxE bit OCx output state

0 Output disabled (OCx=’0’, OCx_EN=’0’)

1 OCx=OCxREF + Polarity, OCx_EN=’1’

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CNT[15:0]

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Bits 15:0 CNT[15:0]: Counter value

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PSC[15:0]

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Bits 15:0 PSC[15:0]: Prescaler value

The counter clock frequency CK_CNT is equal to f

CK_PSC

/ (PSC[15:0] + 1).

PSC contains the value to be loaded into the active prescaler register at each update event.

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ARR[15:0]

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Bits 15:0 ARR[15:0]: Auto-reload value

ARR is the value to be loaded into the actual auto-reload register.

Refer to Section 16.3.1: Time-base unit for more details about ARR update and behavior.

The counter is blocked while the auto-reload value is null.

ST STM32F410 User Manual