ST STM32F410 User Manual

Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401
558/771 RM0401 Rev 3
22.4.11 SMBus specific features
This section is relevant only when SMBus feature is supported. Refer to Section 22.3:
FMPI2C implementation.
Introduction
The System Management Bus (SMBus) is a two-wire interface through which various
devices can communicate with each other and with the rest of the system. It is based on I
2
C
principles of operation. SMBus provides a control bus for system and power management
related tasks.
This peripheral is compatible with the SMBUS specification (http://smbus.org).
The System Management Bus Specification refers to three types of devices.
• A slave is a device that receives or responds to a command.
• A master is a device that issues commands, generates the clocks and terminates the
transfer.
• A host is a specialized master that provides the main interface to the system’s CPU. A
host must be a master-slave and must support the SMBus host notify protocol. Only
one host is allowed in a system.
This peripheral can be configured as master or slave device, and also as a host.
Bus protocols
There are eleven possible command protocols for any given device. A device may use any
or all of the eleven protocols to communicate. The protocols are Quick Command, Send
Byte, Receive Byte, Write Byte, Write Word, Read Byte, Read Word, Process Call, Block
Read, Block Write and Block Write-Block Read Process Call. These protocols should be
implemented by the user software.
For more details of these protocols, refer to SMBus specification (http://smbus.org).
Address resolution protocol (ARP)
SMBus slave address conflicts can be resolved by dynamically assigning a new unique
address to each slave device. In order to provide a mechanism to isolate each device for the
purpose of address assignment each device must implement a unique device identifier
(UDID). This 128-bit number is implemented by software.
This peripheral supports the Address Resolution Protocol (ARP). The SMBus Device
Default Address (0b1100 001) is enabled by setting SMBDEN bit in FMPI2C_CR1 register.
The ARP commands should be implemented by the user software.
Arbitration is also performed in slave mode for ARP support.
For more details of the SMBus Address Resolution Protocol, refer to SMBus specification
(http://smbus.org).
2. t
SYNC1 +
t
SYNC2
minimum value is 4 x t
I2CCLK
= 250 ns. Example with t
SYNC1 +
t
SYNC2
= 1000 ns.
3. t
SYNC1 +
t
SYNC2
minimum value is 4 x t
I2CCLK
= 250 ns. Example with t
SYNC1 +
t
SYNC2
= 750 ns.
4. t
SYNC1 +
t
SYNC2
minimum value is 4 x t
I2CCLK
= 250 ns. Example with t
SYNC1 +
t
SYNC2
= 500 ns.

ST STM32F410 Specifications

General

Brand	ST
Model	STM32F410
Category	Microcontrollers
Language	English