Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0401
682/771 RM0401 Rev 3
25.1.2 SPI extended features
• SPI TI mode support
25.1.3 I2S features
• Half-duplex communication (only transmitter or receiver)
• Master or slave operations
• 8-bit programmable linear prescaler to reach accurate audio sample frequencies (from
8 kHz to 192 kHz)
• Data format may be 16-bit, 24-bit or 32-bit
• Packet frame is fixed to 16-bit (16-bit data frame) or 32-bit (16-bit, 24-bit, 32-bit data
frame) by audio channel
• Programmable clock polarity (steady state)
• Underrun flag in slave transmission mode, overrun flag in reception mode (master and
slave) and Frame Error Flag in reception and transmitter mode (slave only)
• 16-bit register for transmission and reception with one data register for both channel
sides
• Supported I
2
S protocols:
–I
2
S Philips standard
– MSB-Justified standard (Left-Justified)
– LSB-Justified standard (Right-Justified)
– PCM standard (with short and long frame synchronization on 16-bit channel frame
or 16-bit data frame extended to 32-bit channel frame)
• Data direction is always MSB first
• DMA capability for transmission and reception (16-bit wide)
• Master clock can be output to drive an external audio component. Ratio is fixed at
256 × F
S
(where F
S
is the audio sampling frequency)
• I
2
S (I2S1, I2S2 and I2S5) clock can be derived from an external clock mapped on the
I2S_CKIN pin.
25.2 SPI/I2S implementation
This manual describes the full set of features implemented in SPI1, SPI2 and SPI5.
Table 124. STM32F410 SPI implementation
SPI
Features
(1)
1. X = supported.
SPI1 SPI2 SPI5
Hardware CRC calculation X X X
I2S mode XXX
TI mode X X X
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