ST STM32F410 User Manual

Reset and clock control (RCC) RM0401
114/771 RM0401 Rev 3
5.3.7 RCC APB2 peripheral reset register (RCC_APB2RSTR)
Address offset: 0x24
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
SPI5
RST
Res.
TIM11
RST
Res.
TIM9
RST
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res.
SYSCFG
RST
Res.
SPI1
RST
Res. Res. Res.
ADC1
RST
Res. Res.
USART6
RST
USART1
RST
Res. Res. Res.
TIM1
RST
rw rw rw rw rw rw
Bits 31:21 Reserved, must be kept at reset value.
Bit 20 SPI5RST: SPI5RST
This bit is set and cleared by software.
0: does not reset SPI5
1: resets SPI5
Bit 19 Reserved, must be kept at reset value.
Bit 18 TIM11RST: TIM11 reset
Set and cleared by software.
0: does not reset TIM11
1: resets TIM11
Bit 17 Reserved, must be kept at reset value.
Bit 16 TIM9RST: TIM9 reset
Set and cleared by software.
0: does not reset TIM9
1: resets TIM9
Bit 15 Reserved, must be kept at reset value.
Bit 14 SYSCFGRST: System configuration controller reset
Set and cleared by software.
0: does not reset the System configuration controller
1: resets the System configuration controller
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1RST: SPI1 reset
Set and cleared by software.
0: does not reset SPI1
1: resets SPI1
Bit 11 Reserved, must be kept at reset value.
Bits 10:9 Reserved, must be kept at reset value.
Bit 8 ADC1RST: ADC interface reset
Set and cleared by software.
0: does not reset the ADC interface
1: resets the ADC interface

ST STM32F410 Specifications

General

Brand	ST
Model	STM32F410
Category	Microcontrollers
Language	English