RM0401 Rev 3 71/771
RM0401 Power controller (PWR)
90
a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive
an LED).
When the backup domain is supplied by V
BAT
(analog switch connected to V
BAT
because
V
DD
is not present), the following functions are available:
• PC14 and PC15 can be used as LSE pins only
• PC13 can be used as the RTC additional function pin (refer to Table 26: RTC additional
functions for more details about this pin configuration)
Backup domain access
After reset, the backup domain (RTC registers, and RTC backup register) is protected
against possible unwanted write accesses. To enable access to the backup domain,
proceed as follows:
• Access to the RTC and RTC backup registers
1. Enable the power interface clock by setting the PWREN bits in the RCC_APB1ENR
register (see
Section 5.3.9: RCC APB1 peripheral clock enable register
(RCC_APB1ENR))
2. Set the DBP bit in the Section 4.4.1 to enable access to the backup domain
3. Select the RTC clock source: see Section 5.2.8: RTC/AWU clock
4. Enable the RTC clock by programming the RTCEN [15] bit in the Section 5.3.14: RCC
Backup domain control register (RCC_BDCR)
RTC and RTC backup registers
The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time-
of-day clock/calendar, two programmable alarm interrupts, and a periodic programmable
wakeup flag with interrupt capability. The RTC contains 20 backup data registers (80 bytes)
which are reset when a tamper detection event occurs. For more details refer to
Section 21:
Real-time clock (RTC).
4.1.3 Voltage regulator
An embedded linear voltage regulator supplies all the digital circuitries except for the backup
domain and the Standby circuitry. The regulator output voltage is around 1.2
V.
This voltage regulator requires one capacitor to be connected to the dedicated pin, V
CAP_1
.
When activated by software, the voltage regulator is always enabled after Reset. It works in
three different modes depending on the application modes.
• In Run mode, the regulator supplies full power to the 1.2 V domain (core, memories
and digital peripherals). In this mode, the regulator output voltage (around 1.2 V) can
be scaled by software to different voltage values:
Scale 1, scale 2, or scale 3 can be configured through the VOS[1:0] bits of the
PWR_CR register. After reset the VOS register is set to scale 2. When the PLL is
OFF, the voltage regulator is set to scale 3 independently of the VOS register
content. The VOS register content is only taken into account once the PLL is
activated and the HSI or HSE is selected as clock source.
The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency.
• In Stop mode, the main regulator or the low-power regulator supplies low power to the
1.2 V domain, thus preserving the content of registers and internal SRAM. The voltage
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