ST STM32F410 User Manual

RM0401 Rev 3 527/771
RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface
591
22.4.2 FMPI2C pins and internal signals
22.4.3 FMPI2C clock requirements
The FMPI2C kernel is clocked by FMPI2CCLK.
The FMPI2CCLK period t
I2CCLK
must respect the following conditions:
t
I2CCLK
< (t
LOW
- t
filters
) / 4 and t
I2CCLK
< t
HIGH
with:
t
LOW
: SCL low time and t
HIGH
: SCL high time
t
filters:
when enabled, sum of the delays brought by the analog filter and by the digital filter.
Analog filter delay is maximum 260 ns. Digital filter delay is DNF x t
I2CCLK
.
The PCLK clock period t
PCLK
must respect the following condition:
t
PCLK
< 4/3 t
SCL
with t
SCL
: SCL period
Caution: When the FMPI2C kernel is clocked by PCLK, this clock must respect the conditions for
t
I2CCLK
.
Table 85. FMPI2C input/output pins
Pin name Signal type Description
I2C_SDA Bidirectional I2C data
I2C_SCL Bidirectional I2C clock
I2C_SMBA Bidirectional SMBus Alert
Table 86. FMPI2C internal input/output signals
Internal signal name Signal type Description
i2c_ker_ck Input
I2C kernel clock, also named I2CCLK in this
document
i2c_pclk Input I2C APB clock
i2c_it Output
I2C interrupts, refer to Table 99: FMPI2C
Interrupt requests for the full list of interrupt
sources
i2c_rx_dma Output I2C Receive Data DMA request (I2C_RX)
i2c_tx_dma Output I2C Transmit Data DMA request (I2C_TX)

ST STM32F410 Specifications

General

Brand	ST
Model	STM32F410
Category	Microcontrollers
Language	English