ST STM32F410 User Manual

RM0401 Rev 3 37/771
RM0401 System and memory overview
37
2.1.1 I-bus
This bus connects the Instruction bus of the Cortex
®
-M4 with FPU core to the BusMatrix.
This bus is used by the core to fetch instructions. The target of this bus is a memory
containing code (internal Flash memory/SRAM1).
2.1.2 D-bus
This bus connects the databus of the Cortex
®
-M4 with FPU to the BusMatrix. This bus is
used by the core for literal load and debug access. The target of this bus is a memory
containing code or data (internal Flash memory/SRAM1).
2.1.3 S-bus
This bus connects the system bus of the Cortex
®
-M4 with FPU core to a BusMatrix. This
bus is used to access data located in a peripheral or in SRAM1. Instructions may also be
fetch on this bus (less efficient than ICode). The targets of this bus are the internal SRAM1,
the AHB1 peripherals including the APB peripherals, and the AHB2 peripherals.
2.1.4 DMA memory bus
This bus connects the DMA memory bus master interface to the BusMatrix. It is used by the
DMA to perform transfer to/from memories. The targets of this bus are data memories:
internal Flash memory, internal SRAM1 and additionally for S4 the AHB1/AHB2 peripherals
including the APB peripherals.
2.1.5 DMA peripheral bus
This bus connects the DMA peripheral master bus interface to the BusMatrix. This bus is
used by the DMA to access AHB peripherals or to perform memory-to-memory transfers.
The targets of this bus are the AHB and APB peripherals plus data memories: Flash
memory and internal SRAM1.
2.1.6 BusMatrix
The BusMatrix manages the access arbitration between masters. The arbitration uses a
round-robin algorithm.
2.1.7 AHB/APB bridges (APB)
The two AHB/APB bridges, APB1 and APB2, provide full synchronous connections between
the AHB and the two APB buses, allowing flexible selection of the peripheral frequency.
Refer to the device datasheets for more details on APB1 and APB2 maximum frequencies,
and to
Table 1 for the address mapping of AHB and APB peripherals.
After each device reset, all peripheral clocks are disabled (except for the SRAM and Flash
memory interface). Before using a peripheral you have to enable its clock in the
RCC_AHBxENR or RCC_APBxENR register.
Note: When a 16- or an 8-bit access is performed on an APB register, the access is transformed
into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.

ST STM32F410 Specifications

General

Brand	ST
Model	STM32F410
Category	Microcontrollers
Language	English