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RM0401 Rev 3 77/771

RM0401 Power controller (PWR)

Section 5.3.8: RCC AHB1 peripheral clock enable register (RCC_AHB1ENR)).

Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting

the corresponding bit in RCC_AHBxLPENR and RCC_APBxLPENR registers.

4.3.4 Flash memory in low-power mode for code execution from RAM

For applications where the code is executed from RAM, the Flash memory can be put in two

possible low-power mode.

• Stop mode

• Deep-power down mode

Putting the Flash memory in Deep-power down mode allows to achieve the best power

consumption. However the Flash memory wakeup time is the slowest (refer to the

Electrical characteristics section of the datasheet).

From Run mode, the Flash memory can be configured anytime by software to enter any of

these low-power mode.

From Sleep mode, setting the Flash memory low-power down mode must be done before

entering Sleep mode.

The Flash memory wakeup time has to be handled by software counter.

4.3.5 Sleep mode

Entering Sleep mode

The Sleep mode is entered according to Section : Entering low-power mode, when the

SLEEPDEEP bit in the Cortex

-M4 with FPU System Control register is cleared.

Refer to Table 15 and Table 16 for details on how to enter Sleep mode.

Exiting Sleep mode

The Sleep mode is exited according to Section : Exiting low-power mode.

Refer to Table 15 and Table 16 for more details on how to exit Sleep mode.

Table 15. Sleep-now entry and exit

Sleep-now mode Description

Mode entry

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP = 0

– No interrupt (for WFI) or event (for WFE) is pending

Refer to the Cortex

-M4 with FPU System Control register.

On Return from ISR while:

– SLEEPDEEP = 0 and

– SLEEPONEXIT = 1

– No interrupt is pending

Refer to the Cortex

-M4 with FPU System Control register.

ST STM32F410 User Manual

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