ST STM32F410 User Manual

RM0401 Rev 3 545/771
RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface
591
22.4.9 FMPI2C master mode
FMPI2C master initialization
Before enabling the peripheral, the FMPI2C master clock must be configured by setting the
SCLH and SCLL bits in the FMPI2C_TIMINGR register.
The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C
Configuration window.
A clock synchronization mechanism is implemented in order to support multi-master
environment and slave clock stretching.
In order to allow clock synchronization:
• The low level of the clock is counted using the SCLL counter, starting from the SCL low
level internal detection.
• The high level of the clock is counted using the SCLH counter, starting from the SCL
high level internal detection.
The FMPI2C detects its own SCL low level after a
t
SYNC1
delay depending on the SCL falling
edge, SCL input noise filters (analog + digital) and SCL synchronization to the I2CxCLK
clock. The FMPI2C releases SCL to high level once the SCLL counter reaches the value
programmed in the SCLL[7:0] bits in the FMPI2C_TIMINGR register.
The FMPI2C detects its own SCL high level after a
t
SYNC2
delay depending on the SCL rising
edge, SCL input noise filters (analog + digital) and SCL synchronization to I2CxCLK clock.
The FMPI2C ties SCL to low level once the SCLH counter is reached reaches the value
programmed in the SCLH[7:0] bits in the FMPI2C_TIMINGR register.
Consequently the master clock period is:
t
SCL =
t
SYNC1
+ t
SYNC2 +
{[(SCLH+1) + (SCLL+1)] x (PRESC+1) x t
I2CCLK
}
The duration of t
SYNC1
depends on these parameters:
– SCL falling slope
– When enabled, input delay induced by the analog filter.
– When enabled, input delay induced by the digital filter: DNF
x t
I2CCLK
– Delay due to SCL synchronization with FMPI2CCLK clock (2 to 3 FMPI2CCLK
periods)
The duration of t
SYNC2
depends on these parameters:
– SCL rising slope
– When enabled, input delay induced by the analog filter.
– When enabled, input delay induced by the digital filter: DNF
x t
I2CCLK
– Delay due to SCL synchronization with FMPI2CCLK clock (2 to 3 FMPI2CCLK
periods)

ST STM32F410 Specifications

General

Brand	ST
Model	STM32F410
Category	Microcontrollers
Language	English