ST STM32F410 User Manual

Interrupts and events RM0401
206/771 RM0401 Rev 3
9.3 EXTI registers
Refer to Section 1.2: List of abbreviations for registers for a list of abbreviations used in
register descriptions.
9.3.1 Interrupt mask register (EXTI_IMR)
Address offset: 0x00
Reset value: 0x0000 0000
9.3.2 Event mask register (EXTI_EMR)
Address offset: 0x04
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. MR22 MR21 Res. Res. MR18 MR17 MR16
rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:21 MRx: Interrupt mask on line x
0: Interrupt request from line x is masked
1: Interrupt request from line x is not masked
Bits 20-19 Reserved, must be kept at reset value.
Bits 18:0 MRx: Interrupt mask on line x
0: Interrupt request from line x is masked
1: Interrupt request from line x is not masked
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. MR22 MR21 Res. Res. MR18 MR17 MR16
rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:21 MRx: Event mask on line x
0: Event request from line x is masked
1: Event request from line x is not masked
Bits 20-19 Reserved, must be kept at reset value.
Bits 18:0 MRx: Event mask on line x
0: Event request from line x is masked
1: Event request from line x is not masked

ST STM32F410 Specifications

General

Brand	ST
Model	STM32F410
Category	Microcontrollers
Language	English