RM0401 Rev 3 123/771
RM0401 Reset and clock control (RCC)
134
5.3.12 RCC APB1 peripheral clock enable in low power mode register
(RCC_APB1LPENR)
Address offset: 0x60
Reset value: 0x10E2 C80F
Access: no wait state, word, half-word and byte access.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res.
DAC
LPEN
PWR
LPEN
Res. Res. Res.
I2C4
LPEN
Res.
I2C2
LPEN
I2C1
LPEN
Res. Res. Res.
USART2
LPEN
Res.
rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res.
SPI2
LPEN
Res. Res.
WWDG
LPEN
RTCAPB
LPEN
LPTIM1
LPEN
Res. Res. Res. Res.
TIM6
LPEN
TIM5
LPEN
Res. Res. Res.
rw rw rw rw rw rw
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 DACLPEN: DAC interface clock enable during Sleep mode
Set and cleared by software.
0: DAC interface clock disabled during Sleep mode
1: DAC interface clock enabled during Sleep mode
Bit 28 PWRLPEN: Power interface clock enable during Sleep mode
Set and cleared by software.
0: Power interface clock disabled during Sleep mode
1: Power interface clock enabled during Sleep mode
Bits 27:25 Reserved, must be kept at reset value.
Bit 24 I2C4LPEN: I2C4 clock enable during Sleep mode
Set and cleared by software.
0: I2C4 clock disabled during Sleep mode
1: I2C4 clock enabled during Sleep mode
Bit 23 Reserved, must be kept at reset value.
Bit 22 I2C2LPEN: I2C2 clock enable during Sleep mode
Set and cleared by software.
0: I2C2 clock disabled during Sleep mode
1: I2C2 clock enabled during Sleep mode
Bit 21 I2C1LPEN: I2C1 clock enable during Sleep mode
Set and cleared by software.
0: I2C1 clock disabled during Sleep mode
1: I2C1 clock enabled during Sleep mode
Bits 20:18 Reserved, must be kept at reset value.
Bit 17 USART2LPEN: USART2 clock enable during Sleep mode
Set and cleared by software.
0: USART2 clock disabled during Sleep mode
1: USART2 clock enabled during Sleep mode
Bits 16:15 Reserved, must be kept at reset value.
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