RM0401 Rev 3 705/771
RM0401 Serial peripheral interface/ inter-IC sound (SPI/I2S)
731
The I
2
S shares three common pins with the SPI:
• SD: Serial Data (mapped on the MOSI pin) to transmit or receive the two time-
multiplexed data channels (in half-duplex mode only).
• WS: Word Select (mapped on the NSS pin) is the data control signal output in master
mode and input in slave mode.
• CK: Serial Clock (mapped on the SCK pin) is the serial clock output in master mode
and serial clock input in slave mode.
An additional pin can be used when a master clock output is needed for some external
audio devices:
• MCK: Master Clock (mapped separately) is used, when the I
2
S is configured in master
mode (and when the MCKOE bit in the SPIx_I2SPR register is set), to output this
additional clock generated at a preconfigured frequency rate equal to 256 × f
S
, where
f
S
is the audio sampling frequency.
The I
2
S uses its own clock generator to produce the communication clock when it is set in
master mode. This clock generator is also the source of the master clock output. Two
additional registers are available in I
2
S mode. One is linked to the clock generator
configuration SPIx_I2SPR and the other one is a generic I
2
S configuration register
SPIx_I2SCFGR (audio standard, slave/master mode, data format, packet frame, clock
polarity, etc.).
The SPIx_CR1 register and all CRC registers are not used in the I
2
S mode. Likewise, the
SSOE bit in the SPIx_CR2 register and the MODF and CRCERR bits in the SPIx_SR are
not used.
The I
2
S uses the same SPI register for data transfer (SPIx_DR) in 16-bit wide mode.
25.6.2 I2S full-duplex
Figure 253 shows how to perform full-duplex communications using two SPI/I2S instances.
In this case, the WS and CK IOs of both SPI2S must be connected together.
For the master full-duplex mode, one of the SPI2S block must be programmed in master
(I2SCFG = ‘10’ or ‘11’), and the other SPI2S block must be programmed in slave (I2SCFG =
‘00’ or ‘01’). The MCK can be generated or not, depending on the application needs.
For the slave full-duplex mode, both SPI2S blocks must be programmed in slave. One of
them in the slave receiver (I2SCFG = ‘01’), and the other in the slave transmitter (I2SCFG =
‘00’). The master external device then provides the bit clock (CK) and the frame
synchronization (WS).
Note that the full-duplex mode can be used for all the supported standards: I2S Philips, MSB
justified, LSB justified and PCM.
For the full-duplex mode, both SPI2S instances must use the same standard, with the same
parameters: I2SMOD, I2SSTD, CKPOL, PCMSYNC, DATLEN and CHLEN must contain the
same value on both instances.
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