ST STM32F410 User Manual

RM0401 Rev 3 93/771
RM0401 Reset and clock control (RCC)
134
5.1.3 Backup domain reset
The backup domain reset sets all RTC registers and the RCC_BDCR register to their reset
values.
A backup domain reset is generated when one of the following events occurs:
1. Software reset, triggered by setting the BDRST bit in the RCC Backup domain control
register (RCC_BDCR).
2. V
DD
or V
BAT
power on, if both supplies have previously been powered off.
5.2 Clocks
Three different clock sources can be used to drive the system clock (SYSCLK):
• HSI oscillator clock
• HSE oscillator clock
• PLL (PLL) clock
The devices have the two following secondary clock sources:
• 32 kHz low-speed internal RC (LSI RC) which drives the independent watchdog and,
optionally, the RTC used for Auto-wakeup from the Stop/Standby mode.
• 32.768 kHz low-speed external crystal (LSE crystal) which optionally drives the RTC
clock (RTCCLK)

ST STM32F410 Specifications

General

Series	STM32F4
Core	ARM Cortex-M4
Max Clock Speed	100 MHz
Maximum CPU frequency	100 MHz
Program memory size	Up to 128 KB
Program memory type	Flash
SRAM	32 KB
RAM size	32 KB
GPIO Pins	Up to 50
Number of I/Os	Up to 50
ADC Channels	Up to 10
ADC	12-bit
DAC Channels	1
Timers	6
Communication Interfaces	I2C, SPI, USART, USB
Operating voltage	1.7 V to 3.6 V
Operating Temperature	-40°C to 85°C
Package	LQFP64