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RM0401 Rev 3
133/771
RM0401
Reset and clock control (RCC)
134
5.3.19
RCC register map
Ta
b
l
e
23
gives the register map and reset values
T
able 23. RCC register
map and reset values
Addr
.
offset
Register
name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x00
RCC_CR
Res.
Res.
Res.
Res.
Res.
Res.
PLL RDY
PLL ON
Res.
Res.
Res.
Res.
CSSON
HSEBYP
HSERDY
HSEON
HSICAL 7
HSICAL 6
HSICAL 5
HSICAL 4
HSICAL 3
HSICAL 2
HSICAL 1
HSICAL 0
HSITRIM 4
HSITRIM 3
HSITRIM 2
HSITRIM 1
HSITRIM 0
Res.
HSIRDY
HSION
0x04
RCC_
PLLCFGR
PLLR3
PLLR2
PLLR1
PLLQ 3
PLLQ 2
PLLQ 1
PLLQ 0
Res.
PLLSRC
Res.
Res.
Res.
Res.
PLLP 1
PLLP 0
Res.
PLLN 8
PLLN 7
PLLN 6
PLLN 5
PLLN 4
PLLN 3
PLLN 2
PLLN 1
PLLN 0
PLLM 5
PLLM 4
PLLM 3
PLLM 2
PLLM 1
PLLM 0
0x08
RCC_CFGR
MCO2 1
MCO2 0
MCO2PRE2
MCO2PRE1
MCO2PRE0
MCO1PRE2
MCO1PRE1
MCO1PRE0
Res.
MCO1 1
MCO1 0
RTCPRE 4
RTCPRE 3
RTCPRE 2
RTCPRE 1
RTCPRE 0
PPRE2 2
PPRE2 1
PPRE2 0
PPRE1 2
PPRE1 1
PPRE1 0
MCO2EN
MCO1EN
HPRE 3
HPRE 2
HPRE 1
HPRE 0
SWS 1
SWS 0
SW 1
SW 0
0x0C
RCC_CIR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CSSC
Res.
Res.
PLLRDYC
HSERDYC
HSIRDYC
LSERDYC
LSIRDYC
Res.
Res.
Res.
PLLRDYIE
HSERDYIE
HSIRDYIE
LSERDYIE
LSIRDYIE
CSSF
Res.
Res.
PLLRDYF
HSERDYF
HSIRDYF
LSERDYF
LSIRDYF
0x10
RCC_
AHB1RSTR
RNGRST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA2RST
DMA1RST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CRCRST
Res.
Res.
Res.
Res.
GPIOHRST
Res.
Res.
Res.
Res.
GPIOCRST
GPIOBR
ST
GPIOAR
ST
0x14 to
0x1C
Reserved
0x20
RCC_
APB1RSTR
Res.
Res.
DACRST
PWRRST
Res.
Res.
Res.
I2C4RST
.
Res.
I2C2RST
I2C1RST
Res.
Res.
Res.
USART2RST
Res.
Res.
SPI2RST
Res.
Res.
WWDGRST
Res.
LPTIM1R
ST
Res.
Res.
Res.
Res.
TIM6RST
TIM5RST
Res.
Res.
Res.
0x24
RCC_
APB2RSTR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SPI5RST
Res.
TIM1
1RST
Res.
TIM9RST
Res.
SYSCFGRST
Res.
SPI1RST
Res.
Res.
Res.
ADC1RST
Res.
USART6RST
USART1RST
Res.
Res.
Res.
TIM1RST
0x28 to
0x2C
Reserved
0x30
RCC_
AHB1ENR
RNGEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA2EN
DMA1EN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CRCEN
Res.
Res.
Res.
Res.
GPIOHEN
Res.
Res.
Res.
Res.
GPIOCEN
GPIOBEN
GPIOAEN
0x34 to
0x3C
Reserved
0x40
RCC_
APB1ENR
Res.
Res.
DACEN
PWREN
Res.
Res.
Res.
I2C4EN
Res.
I2C2EN
I2C1EN
Res.
Res.
Res.
USART2EN
Res.
Res.
SPI2EN
Res.
Res.
WWDGEN
RTCAPBEN
.
LPTIM1EN
Res.
Res.
Res.
Res.
TIM6E
N
TIM5E
N
Res.
Res.
Res.
0x44
RCC_
APB2ENR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SPI5EN
Res.
TIM1
1EN
Res.
TIM9EN
EXTIEN
SYSCFGEN
Res.
SPI1EN
Res.
Res.
Res.
ADC1EN
Res.
Res.
USART6EN
USART1EN
Res.
Res.
Res.
TIM1EN
0x48 to
0x4C
Reserved
132
134
Table of Contents
Default Chapter
2
Table of Contents
2
SYSCFG External Interrupt Configuration Register
4
Documentation Conventions
34
General Information
34
List of Abbreviations for Registers
34
Glossary
35
Availability of Peripherals
35
System and Memory Overview
36
System Architecture
36
Figure 1. System Architecture
36
AHB/APB Bridges (APB)
37
Busmatrix
37
D-Bus
37
DMA Memory Bus
37
DMA Peripheral Bus
37
I-Bus
37
S-Bus
37
Memory Organization
38
Introduction
38
Memory Map and Register Boundary Addresses
38
Figure 2. Memory Map
38
Table 1. Register Boundary Addresses
39
Embedded SRAM
41
Flash Memory Overview
41
Bit Banding
42
Boot Configuration
43
Table 2. Boot Modes
43
Table 3. Embedded Bootloader Interfaces
43
Table 4. Memory Mapping Vs. Boot Mode/Physical Remap in STM32F410
44
Embedded Flash Memory Interface
45
Introduction
45
Main Features
45
Figure 3. Flash Memory Interface Connection Inside System Architecture
45
Embedded Flash Memory
46
Table 5. Flash Module Organization
46
Read Interface
47
Relation between CPU Clock Frequency and Flash Memory Read Time
47
Table 6. Number of Wait States According to CPU Clock (HCLK) Frequency
47
Adaptive Real-Time Memory Accelerator (ART Accelerator™)
48
Figure 4. Sequential 32-Bit Instruction Execution
49
Erase and Program Operations
50
Unlocking the Flash Control Register
50
Program/Erase Parallelism
51
Erase
51
Table 7. Program/Erase Parallelism
51
Programming
52
Interrupts
53
Option Bytes
53
Description of User Option Bytes
53
Table 8. Flash Interrupt Request
53
Table 9. Option Byte Organization
53
Table 10. Description of the Option Bytes
54
Programming User Option Bytes
55
Read Protection (RDP)
55
Write Protections
57
Table 11. Access Versus Read Protection Level
57
Figure 5. RDP Levels
57
Proprietary Code Readout Protection (PCROP)
58
Figure 6. PCROP Levels
59
One-Time Programmable Bytes
60
Table 12. OTP Area Organization
60
Flash Interface Registers
61
Flash Access Control Register (FLASH_ACR)
61
Flash Key Register (FLASH_KEYR)
62
Flash Option Key Register (FLASH_OPTKEYR)
62
Flash Status Register (FLASH_SR)
63
Flash Control Register (FLASH_CR)
64
Flash Option Control Register (FLASH_OPTCR)
65
Flash Interface Register Map
68
Table 13. Flash Register Map and Reset Values
68
Power Controller (PWR)
69
Power Supplies
69
Figure 7. Power Supply Overview
69
Battery Backup Domain
70
Independent A/D Converter Supply and Reference Voltage
70
Voltage Regulator
71
Power Supply Supervisor
72
Power-On Reset (Por)/Power-Down Reset (PDR)
72
Figure 8. Power-On Reset/Power-Down Reset Waveform
72
Brownout Reset (BOR)
73
Figure 9. BOR Thresholds
73
Programmable Voltage Detector (PVD)
74
Low-Power Modes
74
Figure 10. PVD Thresholds
74
Optimizing PLL VCO Frequency
76
Peripheral Clock Gating
76
Slowing down System Clocks
76
Table 14. Low-Power Mode Summary
76
Flash Memory in Low-Power Mode for Code Execution from RAM
77
Sleep Mode
77
Table 15. Sleep-Now Entry and Exit
77
Batch Acquisition Mode
78
Table 16. Sleep-On-Exit Entry and Exit
78
Stop Mode
79
Table 17. BAM-Now Entry and Exit
79
Table 18. BAM-On-Exit Entry and Exit
79
Table 19. Stop Operating Modes
80
Table 20. Stop Mode Entry and Exit
81
Standby Mode
82
Programming the RTC Alternate Functions to Wake up the Device from the Stop and Standby Modes
83
Table 21. Standby Mode Entry and Exit
83
Power Control Registers
86
PWR Power Control Register (PWR_CR)
86
PWR Power Control/Status Register (PWR_CSR)
88
PWR Register Map
90
Table 22. PWR - Register Map and Reset Values
90
Reset and Clock Control (RCC)
91
Reset
91
System Reset
91
Power Reset
92
Figure 11. Simplified Diagram of the Reset Circuit
92
Backup Domain Reset
93
Clocks
93
Figure 12. Clock Tree
94
Figure 13. HSE/ LSE Clock Sources
96
HSE Clock
96
HSI Clock
97
LSE Clock
97
PLL Configuration
97
Clock Security System (CSS)
98
LSI Clock
98
System Clock (SYSCLK) Selection
98
RTC/AWU Clock
99
Watchdog Clock
99
Clock-Out Capability
100
Internal/External Clock Measurement Using TIM5/TIM11
100
Figure 14. Frequency Measurement with TIM5 in Input Capture Mode
101
Figure 15. Frequency Measurement with TIM11 in Input Capture Mode
101
RCC Registers
102
RCC Clock Control Register (RCC_CR)
102
RCC PLL Configuration Register (RCC_PLLCFGR)
104
RCC Clock Configuration Register (RCC_CFGR)
106
RCC Clock Interrupt Register (RCC_CIR)
109
RCC AHB1 Peripheral Reset Register (RCC_AHB1RSTR)
111
RCC APB1 Peripheral Reset Register for (RCC_APB1RSTR)
112
RCC APB2 Peripheral Reset Register (RCC_APB2RSTR)
114
RCC AHB1 Peripheral Clock Enable Register (RCC_AHB1ENR)
116
RCC APB1 Peripheral Clock Enable Register (RCC_APB1ENR)
117
RCC APB2 Peripheral Clock Enable Register (RCC_APB2ENR)
119
RCC AHB1 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB1LPENR)
121
RCC APB1 Peripheral Clock Enable in Low Power Mode Register (RCC_APB1LPENR)
123
RCC APB2 Peripheral Clock Enabled in Low Power Mode Register (RCC_APB2LPENR)
125
RCC Backup Domain Control Register (RCC_BDCR)
127
RCC Clock Control & Status Register (RCC_CSR)
128
RCC Spread Spectrum Clock Generation Register (RCC_SSCGR)
130
RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR)
131
RCC Dedicated Clocks Configuration Register 2 (RCC_DCKCFGR2)
132
RCC Register Map
133
Table 23. RCC Register Map and Reset Values
133
General-Purpose I/Os (GPIO)
135
GPIO Introduction
135
GPIO Main Features
135
GPIO Functional Description
135
Figure 16. Basic Structure of a Five-Volt Tolerant I/O Port Bit
136
Table 24. Port Bit Configuration Table
136
General-Purpose I/O (GPIO)
137
I/O Pin Multiplexer and Mapping
138
Table 25. Flexible SWJ-DP Pin Assignment
139
Figure 17. Selecting an Alternate Function
140
I/O Port Control Registers
140
GPIO Locking Mechanism
141
I/O Data Bitwise Handling
141
I/O Port Data Registers
141
External Interrupt/Wakeup Lines
142
Figure 18. Input Floating/Pull Up/Pull down Configurations
142
I/O Alternate Function Input/Output
142
Input Configuration
142
Alternate Function Configuration
143
Figure 19. Output Configuration
143
Output Configuration
143
Analog Configuration
144
Figure 20. Alternate Function Configuration
144
Figure 21. High Impedance-Analog Configuration
144
Selection of RTC Additional Functions
145
Table 26. RTC Additional Functions
145
Using the OSC32_IN/OSC32_OUT Pins as GPIO PC14/PC15
145
Port Pins
145
Using the OSC_IN/OSC_OUT Pins as GPIO PH0/PH1 Port Pins
145
GPIO Registers
147
GPIO Port Mode Register (Gpiox_Moder) (X = A..C and H
147
GPIO Port Output Type Register (Gpiox_Otyper)
147
(X = a
147
GPIO Port Output Speed Register (Gpiox_Ospeedr)
148
(X = a
148
GPIO Port Pull-Up/Pull-Down Register (Gpiox_Pupdr)
148
GPIO Port Input Data Register (Gpiox_Idr) (X = A..C and H
149
GPIO Port Output Data Register (Gpiox_Odr) (X = A..C and H
149
GPIO Port Bit Set/Reset Register (Gpiox_Bsrr) (X = A..C and H
149
GPIO Port Configuration Lock Register (Gpiox_Lckr)
150
(X = a
150
GPIO Alternate Function Low Register (Gpiox_Afrl) (X = A..C and H)
151
(X = a
152
GPIO Register Map
152
Table 27. GPIO Register Map and Reset Values
152
System Configuration Controller (SYSCFG)
155
I/O Compensation Cell
155
SYSCFG Registers
155
SYSCFG Memory Remap Register (SYSCFG_MEMRMP)
155
SYSCFG Peripheral Mode Configuration Register (SYSCFG_PMC)
156
SYSCFG External Interrupt Configuration Register 1
157
(Syscfg_Exticr1)
157
(Syscfg_Exticr2)
157
SYSCFG External Interrupt Configuration Register 3
158
(Syscfg_Exticr3)
158
(Syscfg_Exticr4)
158
SYSCFG Configuration Register 2 (SYSCFG_CFGR2)
159
Compensation Cell Control Register (SYSCFG_CMPCR)
159
Compensation Cell Control Register (SYSCFG_CFGR)
160
SYSCFG Register Map
161
Table 28. SYSCFG Register Map and Reset Values
161
Direct Memory Access Controller (DMA)
162
DMA Introduction
162
DMA Main Features
162
DMA Functional Description
164
DMA Block Diagram
164
DMA Overview
164
Figure 22. DMA Block Diagram
164
DMA Transactions
165
Figure 23. System Implementation of the Two DMA Controllers
165
Channel Selection
166
Table 29. DMA1 Request Mapping
166
Figure 24. Channel Selection
166
Arbiter
167
DMA Streams
167
Table 30. DMA2 Request Mapping
167
Source, Destination and Transfer Modes
168
Table 31. Source and Destination Address
168
Figure 25. Peripheral-To-Memory Mode
169
Figure 26. Memory-To-Peripheral Mode
170
Pointer Incrementation
171
Figure 27. Memory-To-Memory Mode
171
Circular Mode
172
Double-Buffer Mode
172
Programmable Data Width, Packing/Unpacking, Endianness
173
Table 32. Source and Destination Address Registers in Double-Buffer Mode (DBM = 1)
173
Table 33. Packing/Unpacking and Endian Behavior (Bit PINC = MINC = 1)
174
Table 34. Restriction on NDT Versus PSIZE and MSIZE
174
Single and Burst Transfers
175
Fifo
175
Figure 28. FIFO Structure
175
Table 35. FIFO Threshold Configurations
176
DMA Transfer Completion
178
DMA Transfer Suspension
179
Flow Controller
179
Summary of the Possible DMA Configurations
180
Table 36. Possible DMA Configurations
180
Stream Configuration Procedure
181
Error Management
182
DMA Interrupts
183
Table 37. DMA Interrupt Requests
183
DMA Registers
184
DMA Low Interrupt Status Register (DMA_LISR)
184
DMA High Interrupt Status Register (DMA_HISR)
185
DMA Low Interrupt Flag Clear Register (DMA_LIFCR)
186
DMA High Interrupt Flag Clear Register (DMA_HIFCR)
186
DMA Stream X Configuration Register (Dma_Sxcr)
187
DMA Stream X Number of Data Register (Dma_Sxndtr)
190
DMA Stream X Peripheral Address Register (Dma_Sxpar)
191
DMA Stream X Memory 0 Address Register (Dma_Sxm0Ar)
191
DMA Stream X Memory 1 Address Register (Dma_Sxm1Ar)
191
DMA Stream X FIFO Control Register (Dma_Sxfcr)
192
DMA Register Map
194
Table 38. DMA Register Map and Reset Values
194
Interrupts and Events
198
Nested Vectored Interrupt Controller (NVIC)
198
NVIC Features
198
Systick Calibration Value Register
198
Interrupt and Exception Vectors
198
External Interrupt/Event Controller (EXTI)
198
Table 39. Vector Table
198
EXTI Main Features
202
EXTI Block Diagram
203
Figure 29. External Interrupt/Event Controller Block Diagram
203
Functional Description
203
Wakeup Event Management
203
External Interrupt/Event Line Mapping
205
Figure 30. External Interrupt/Event GPIO Mapping
205
EXTI Registers
206
Interrupt Mask Register (EXTI_IMR)
206
Event Mask Register (EXTI_EMR)
206
Rising Trigger Selection Register (EXTI_RTSR)
207
Falling Trigger Selection Register (EXTI_FTSR)
207
Software Interrupt Event Register (EXTI_SWIER)
208
Pending Register (EXTI_PR)
208
EXTI Register Map
210
Table 40. External Interrupt/Event Controller Register Map and Reset Values
210
CRC Calculation Unit
211
CRC Introduction
211
CRC Main Features
211
CRC Functional Description
211
Figure 31. CRC Calculation Unit Block Diagram
211
CRC Registers
212
Data Register (CRC_DR)
212
Independent Data Register (CRC_IDR)
213
Control Register (CRC_CR)
213
CRC Register Map
214
Table 41. CRC Calculation Unit Register Map and Reset Values
214
Analog-To-Digital Converter (ADC)
215
ADC Introduction
215
ADC Main Features
215
ADC Functional Description
215
Figure 32. Single ADC Block Diagram
216
ADC Clock
217
ADC On-Off Control
217
Channel Selection
217
Table 42. ADC Pins
217
Continuous Conversion Mode
218
Single Conversion Mode
218
Analog Watchdog
219
Figure 33. Timing Diagram
219
Figure 34. Analog Watchdog's Guarded Area
219
Timing Diagram
219
Injected Channel Management
220
Table 43. Analog Watchdog Channel Selection
220
Discontinuous Mode
221
Figure 35. Injected Conversion Latency
221
Scan Mode
220
Data Alignment
222
Channel-Wise Programmable Sampling Time
223
Figure 36. Right Alignment of 12-Bit Data
223
Figure 37. Left Alignment of 12-Bit Data
223
Figure 38. Left Alignment of 6-Bit Data
223
Conversion on External Trigger and Trigger Polarity
224
Table 44. Configuring the Trigger Polarity
224
Table 45. External Trigger for Regular Channels
224
Data Management
225
Using the DMA
225
Table 46. External Trigger for Injected Channels
225
Managing a Sequence of Conversions Without Using the DMA
226
Conversions Without DMA and Without Overrun Detection
226
Fast Conversion Mode
225
Temperature Sensor
226
Figure 39. Temperature Sensor and VREFINT Channel Block Diagram
227
ADC Interrupts
228
Battery Charge Monitoring
228
Table 47. ADC Interrupts
228
ADC Registers
229
ADC Status Register (ADC_SR)
229
ADC Control Register 1 (ADC_CR1)
230
ADC Control Register 2 (ADC_CR2)
232
ADC Sample Time Register 1 (ADC_SMPR1)
234
ADC Sample Time Register 2 (ADC_SMPR2)
234
ADC Injected Channel Data Offset Register X (Adc_Jofrx) (X=1
235
ADC Watchdog Higher Threshold Register (ADC_HTR)
235
ADC Watchdog Lower Threshold Register (ADC_LTR)
235
ADC Regular Sequence Register 1 (ADC_SQR1)
236
ADC Regular Sequence Register 2 (ADC_SQR2)
237
ADC Regular Sequence Register 3 (ADC_SQR3)
237
ADC Injected Sequence Register (ADC_JSQR)
238
ADC Injected Data Register X (Adc_Jdrx) (X= 1
238
ADC Regular Data Register (ADC_DR)
239
ADC Common Status Register (ADC_CSR)
239
ADC Common Control Register (ADC_CCR)
240
11.12.17 ADC Register Map
241
Table 48. ADC Global Register Map
241
Table 49. ADC Register Map and Reset Values
241
Table 50. ADC Register Map and Reset Values (Common ADC Registers)
242
Digital-To-Analog Converter (DAC)
243
Introduction
243
DAC Main Features
243
DAC Output Buffer Enable
244
Table 51. DAC Pins
244
Figure 40. DAC Channel Block Diagram
244
DAC Channel Enable
245
Single Mode Functional Description
245
DAC Data Format
245
DAC Channel Conversion
245
Figure 41. Data Registers in Single DAC Channel Mode
245
Figure 42. Timing Diagram for Conversion with Trigger Disabled TEN = 0
246
DAC Output Voltage
247
DAC Trigger Selection
247
Table 52. External Triggers
247
Noise Generation
248
Figure 43. DAC LFSR Register Calculation Algorithm
248
Figure 44. DAC Conversion (SW Trigger Enabled) with LFSR Wave Generation
248
Triangle-Wave Generation
249
Figure 45. DAC Triangle Wave Generation
249
Figure 46. DAC Conversion (SW Trigger Enabled) with Triangle Wave Generation
249
DMA Request
250
DAC Registers
251
DAC Control Register (DAC_CR)
251
DAC Software Trigger Register (DAC_SWTRIGR)
253
DAC Channel1 12-Bit Right-Aligned Data Holding Register (DAC_DHR12R1)
253
DAC Channel1 12-Bit Left-Aligned Data Holding Register
254
(Dac_Dhr12L1)
254
DAC Channel1 8-Bit Right-Aligned Data Holding Register (DAC_DHR8R1)
254
DAC Channel1 Data Output Register (DAC_DOR1)
254
DAC Status Register (DAC_SR)
255
DAC Register Map
256
Table 53. DAC Register Map and Reset Values
256
True Random Number Generator (RNG)
257
Introduction
257
RNG Main Features
257
RNG Functional Description
258
RNG Block Diagram
258
RNG Internal Signals
258
Table 54. RNG Internal Input/Output Signals
258
Figure 47. RNG Block Diagram
258
Random Number Generation
259
Figure 48. Entropy Source Model
259
RNG Initialization
261
RNG Operation
261
RNG Clocking
262
Error Management
262
RNG Low-Power Usage
263
RNG Interrupts
263
RNG Processing Time
263
Table 55. RNG Interrupt Requests
263
Entropy Source Validation
264
Introduction
264
Validation Conditions
264
RNG Registers
265
RNG Control Register (RNG_CR)
265
RNG Status Register (RNG_SR)
266
RNG Data Register (RNG_DR)
267
RNG Register Map
268
Table 56. RNG Register Map and Reset Map
268
Advanced-Control Timers (TIM1)
269
TIM1 Introduction
269
TIM1 Main Features
269
Figure 49. Advanced-Control Timer Block Diagram
270
TIM1 Functional Description
271
Time-Base Unit
271
Figure 50. Counter Timing Diagram with Prescaler Division Change from 1 to 2
272
Figure 51. Counter Timing Diagram with Prescaler Division Change from 1 to 4
272
Counter Modes
273
Figure 52. Counter Timing Diagram, Internal Clock Divided by 1
273
Figure 53. Counter Timing Diagram, Internal Clock Divided by 2
274
Figure 54. Counter Timing Diagram, Internal Clock Divided by 4
274
Figure 55. Counter Timing Diagram, Internal Clock Divided by N
274
Figure 56. Counter Timing Diagram, Update Event When ARPE=0
275
Figure 57. Counter Timing Diagram, Update Event When ARPE=1
275
Figure 58. Counter Timing Diagram, Internal Clock Divided by 1
277
Figure 59. Counter Timing Diagram, Internal Clock Divided by 2
277
Figure 60. Counter Timing Diagram, Internal Clock Divided by 4
278
Figure 61. Counter Timing Diagram, Internal Clock Divided by N
278
Figure 62. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used
279
Figure 63. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr = 0X6
280
Figure 64. Counter Timing Diagram, Internal Clock Divided by 2
280
Figure 65. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
281
Figure 66. Counter Timing Diagram, Internal Clock Divided by N
281
Repetition Counter
282
Figure 67. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
282
Figure 68. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
282
Figure 69. Update Rate Examples Depending on Mode and Timx_Rcr Register Settings
283
Clock Selection
284
Figure 70. Control Circuit in Normal Mode, Internal Clock Divided by 1
284
Figure 71. TI2 External Clock Connection Example
285
Figure 72. Control Circuit in External Clock Mode 1
286
Figure 73. External Trigger Input Block
286
Capture/Compare Channels
287
Figure 74. Control Circuit in External Clock Mode 2
287
Figure 75. Capture/Compare Channel (Example: Channel 1 Input Stage)
288
Figure 76. Capture/Compare Channel 1 Main Circuit
288
Figure 77. Output Stage of Capture/Compare Channel (Channels 1 to 3)
289
Figure 78. Output Stage of Capture/Compare Channel (Channel 4)
289
Input Capture Mode
290
PWM Input Mode
291
Forced Output Mode
291
Figure 79. PWM Input Mode Timing
291
Output Compare Mode
292
PWM Mode
293
Figure 80. Output Compare Mode, Toggle on OC1
293
Figure 81. Edge-Aligned PWM Waveforms (ARR=8)
294
Figure 82. Center-Aligned PWM Waveforms (ARR=8)
295
Complementary Outputs and Dead-Time Insertion
296
Figure 83. Complementary Output with Dead-Time Insertion
297
Figure 84. Dead-Time Waveforms with Delay Greater than the Negative Pulse
297
Figure 85. Dead-Time Waveforms with Delay Greater than the Positive Pulse
297
Using the Break Function
298
Figure 86. Output Behavior in Response to a Break
300
Clearing the Ocxref Signal on an External Event
301
Figure 87. Clearing Timx Ocxref
301
6-Step PWM Generation
302
Figure 88. 6-Step Generation, COM Example (OSSR=1)
302
One-Pulse Mode
303
Figure 89. Example of One Pulse Mode
303
Encoder Interface Mode
304
Table 57. Counting Direction Versus Encoder Signals
305
Figure 90. Example of Counter Operation in Encoder Interface Mode
306
Figure 91. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
306
Timer Input XOR Function
307
Interfacing with Hall Sensors
307
Figure 92. Example of Hall Sensor Interface
308
Timx and External Trigger Synchronization
309
Figure 93. Control Circuit in Reset Mode
309
Figure 94. Control Circuit in Gated Mode
310
Figure 95. Control Circuit in Trigger Mode
311
Debug Mode
312
Figure 96. Control Circuit in External Clock Mode 2 + Trigger Mode
312
TIM1 Registers
313
TIM1 Control Register 1 (Timx_Cr1)
313
TIM1 Control Register 2 (Timx_Cr2)
314
TIM1 Slave Mode Control Register (Timx_Smcr)
316
TIM1 Dma/Interrupt Enable Register (Timx_Dier)
318
Table 58. Timx Internal Trigger Connection
318
TIM1 Status Register (Timx_Sr)
320
TIM1 Event Generation Register (Timx_Egr)
321
TIM1 Capture/Compare Mode Register 1 (Timx_Ccmr1)
323
TIM1 Capture/Compare Mode Register 2 (Timx_Ccmr2)
326
TIM1 Capture/Compare Enable Register (Timx_Ccer)
327
Table 59. Output Control Bits for Complementary Ocx and Ocxn Channels
330
With Break Feature
330
TIM1 Counter (Timx_Cnt)
331
TIM1 Prescaler (Timx_Psc)
331
TIM1 Auto-Reload Register (Timx_Arr)
331
TIM1 Repetition Counter Register (Timx_Rcr)
332
TIM1 Capture/Compare Register 1 (Timx_Ccr1)
332
TIM1 Capture/Compare Register 2 (Timx_Ccr2)
333
TIM1 Capture/Compare Register 3 (Timx_Ccr3)
333
TIM1 Capture/Compare Register 4 (Timx_Ccr4)
334
TIM1 Break and Dead-Time Register (Timx_Bdtr)
334
TIM1 DMA Control Register (Timx_Dcr)
336
TIM1 DMA Address for Full Transfer (Timx_Dmar)
337
TIM1 Register Map
338
Table 60. TIM1 Register Map and Reset Values
338
General-Purpose Timers (TIM5)
340
TIM5 Introduction
340
TIM5 Main Features
340
TIM5 Functional Description
341
Time-Base Unit
341
Figure 97. General-Purpose Timer Block Diagram
341
Figure 98. Counter Timing Diagram with Prescaler Division Change from 1 to 2
342
Counter Modes
343
Figure 99. Counter Timing Diagram with Prescaler Division Change from 1 to 4
343
Figure 100. Counter Timing Diagram, Internal Clock Divided by 1
344
Figure 101. Counter Timing Diagram, Internal Clock Divided by 2
344
Figure 102. Counter Timing Diagram, Internal Clock Divided by 4
344
Figure 103. Counter Timing Diagram, Internal Clock Divided by N
345
Figure 104. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
345
Figure 105. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)
346
Figure 106. Counter Timing Diagram, Internal Clock Divided by 1
347
Figure 107. Counter Timing Diagram, Internal Clock Divided by 2
347
Figure 108. Counter Timing Diagram, Internal Clock Divided by 4
347
Figure 109. Counter Timing Diagram, Internal Clock Divided by N
348
Figure 110. Counter Timing Diagram, Update Event
348
Figure 111. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr=0X6
349
Figure 112. Counter Timing Diagram, Internal Clock Divided by 2
350
Figure 113. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
350
Figure 114. Counter Timing Diagram, Internal Clock Divided by N
350
Clock Selection
351
Figure 115. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
351
Figure 116. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
351
Figure 117. Control Circuit in Normal Mode, Internal Clock Divided by 1
352
Figure 118. TI2 External Clock Connection Example
352
Capture/Compare Channels
353
Figure 119. Control Circuit in External Clock Mode 1
353
Figure 120. Capture/Compare Channel (Example: Channel 1 Input Stage)
354
Figure 121. Capture/Compare Channel 1 Main Circuit
354
Input Capture Mode
355
Figure 122. Output Stage of Capture/Compare Channel (Channel 1)
355
PWM Input Mode
356
Forced Output Mode
357
Figure 123. PWM Input Mode Timing
357
Output Compare Mode
358
PWM Mode
359
Figure 124. Output Compare Mode, Toggle on OC1
359
Figure 125. Edge-Aligned PWM Waveforms (ARR=8)
360
Figure 126. Center-Aligned PWM Waveforms (ARR=8)
361
One-Pulse Mode
362
Figure 127. Example of One-Pulse Mode
362
Encoder Interface Mode
363
Table 61. Counting Direction Versus Encoder Signals
364
Figure 128. Example of Counter Operation in Encoder Interface Mode
365
Figure 129. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
365
Timer Input XOR Function
366
Timers and External Trigger Synchronization
366
Figure 130. Control Circuit in Reset Mode
366
Figure 131. Control Circuit in Gated Mode
367
Debug Mode
368
Figure 132. Control Circuit in Trigger Mode
368
TIM5 Registers
369
Timx Control Register 1 (Timx_Cr1)
369
Timx Control Register 2 (Timx_Cr2)
371
Timx Slave Mode Control Register (Timx_Smcr)
372
Timx Dma/Interrupt Enable Register (Timx_Dier)
373
Table 62. Timx Internal Trigger Connection
373
Timx Status Register (Timx_Sr)
374
Timx Event Generation Register (Timx_Egr)
376
Timx Capture/Compare Mode Register 1 (Timx_Ccmr1)
377
Timx Capture/Compare Mode Register 2 (Timx_Ccmr2)
380
Timx Capture/Compare Enable Register (Timx_Ccer)
381
Table 63. Output Control Bit for Standard Ocx Channels
382
Timx Counter (Timx_Cnt)
383
Timx Prescaler (Timx_Psc)
383
Timx Auto-Reload Register (Timx_Arr)
383
Timx Capture/Compare Register 1 (Timx_Ccr1)
384
Timx Capture/Compare Register 2 (Timx_Ccr2)
384
Timx Capture/Compare Register 3 (Timx_Ccr3)
384
Timx Capture/Compare Register 4 (Timx_Ccr4)
385
Timx DMA Control Register (Timx_Dcr)
385
Timx DMA Address for Full Transfer (Timx_Dmar)
386
TIM5 Option Register (TIM5_OR)
387
Timx Register Map
388
Table 64. TIM5 Register Map and Reset Values
388
General-Purpose Timers (TIM9 and TIM11)
390
TIM9 and TIM11 Introduction
390
TIM9 and TIM11 Main Features
390
TIM9 Main Features
390
TIM11 Main Features
391
Figure 133. General-Purpose Timer Block Diagram (TIM9)
391
Figure 134. General-Purpose Timer Block Diagram (TIM11)
392
TIM9 and TIM11 Functional Description
393
Time-Base Unit
393
Figure 135. Counter Timing Diagram with Prescaler Division Change from 1 to 2
394
Figure 136. Counter Timing Diagram with Prescaler Division Change from 1 to 4
394
Counter Modes
395
Figure 137. Counter Timing Diagram, Internal Clock Divided by 1
395
Figure 138. Counter Timing Diagram, Internal Clock Divided by 2
396
Figure 139. Counter Timing Diagram, Internal Clock Divided by 4
396
Figure 140. Counter Timing Diagram, Internal Clock Divided by N
396
Figure 141. Counter Timing Diagram, Update Event When ARPE=0
397
Figure 142. Counter Timing Diagram, Update Event When ARPE=1
397
Clock Selection
398
Figure 143. Control Circuit in Normal Mode, Internal Clock Divided by 1
398
Figure 144. TI2 External Clock Connection Example
399
Figure 145. Control Circuit in External Clock Mode 1
399
Capture/Compare Channels
400
Figure 146. Capture/Compare Channel (Example: Channel 1 Input Stage)
400
Input Capture Mode
401
Figure 147. Capture/Compare Channel 1 Main Circuit
401
Figure 148. Output Stage of Capture/Compare Channel (Channel 1)
401
PWM Input Mode (Only for TIM9)
402
Forced Output Mode
403
Figure 149. PWM Input Mode Timing
403
Output Compare Mode
404
PWM Mode
405
Figure 150. Output Compare Mode, Toggle on OC1
405
One-Pulse Mode
406
Figure 151. Edge-Aligned PWM Waveforms (ARR=8)
406
Figure 152. Example of One Pulse Mode
407
TIM9 External Trigger Synchronization
408
Figure 153. Control Circuit in Reset Mode
409
Figure 154. Control Circuit in Gated Mode
410
Figure 155. Control Circuit in Trigger Mode
410
Debug Mode
411
TIM9 Registers
411
TIM9 Control Register 1 (Timx_Cr1)
411
TIM9 Slave Mode Control Register (Timx_Smcr)
413
TIM9 Interrupt Enable Register (Timx_Dier)
414
Table 65. Timx Internal Trigger Connections
414
TIM9 Status Register (Timx_Sr)
415
TIM9 Event Generation Register (Timx_Egr)
417
TIM9 Capture/Compare Mode Register 1 (Timx_Ccmr1)
417
TIM9 Capture/Compare Enable Register (Timx_Ccer)
421
TIM9 Counter (Timx_Cnt)
422
TIM9 Prescaler (Timx_Psc)
422
TIM9 Auto-Reload Register (Timx_Arr)
422
Table 66. Output Control Bit for Standard Ocx Channels
422
TIM9 Capture/Compare Register 1 (Timx_Ccr1)
423
TIM9 Capture/Compare Register 2 (Timx_Ccr2)
423
TIM9 Register Map
424
Table 67. TIM9 Register Map and Reset Values
424
TIM11 Registers
426
TIM11 Control Register 1 (Timx_Cr1)
426
TIM11 Interrupt Enable Register (Timx_Dier)
427
TIM11 Status Register (Timx_Sr)
427
TIM11 Event Generation Register (Timx_Egr)
428
TIM11 Capture/Compare Mode Register 1
429
(Timx_Ccmr1)
429
TIM11 Capture/Compare Enable Register
432
(Timx_Ccer)
432
Table 68. Output Control Bit for Standard Ocx Channels
432
TIM11 Counter (Timx_Cnt)
433
TIM11 Prescaler (Timx_Psc)
433
TIM11 Auto-Reload Register (Timx_Arr)
433
TIM11 Capture/Compare Register 1 (Timx_Ccr1)
434
TIM11 Option Register 1 (TIM11_OR)
434
TIM11 Register Map
435
Table 69. TIM11 Register Map and Reset Values
435
Basic Timers (TIM6)
437
Introduction
437
TIM6 Main Features
437
Figure 156. Basic Timer Block Diagram
437
TIM6 Functional Description
438
Time-Base Unit
438
Figure 157. Counter Timing Diagram with Prescaler Division Change from 1 to 2
439
Figure 158. Counter Timing Diagram with Prescaler Division Change from 1 to 4
439
Counting Mode
440
Figure 159. Counter Timing Diagram, Internal Clock Divided by 1
440
Figure 160. Counter Timing Diagram, Internal Clock Divided by 2
441
Figure 161. Counter Timing Diagram, Internal Clock Divided by 4
441
Figure 162. Counter Timing Diagram, Internal Clock Divided by N
442
Clock Source
443
Debug Mode
444
Figure 165. Control Circuit in Normal Mode, Internal Clock Divided by 1
444
TIM6 Registers
445
TIM6 Control Register 1 (Timx_Cr1)
445
TIM6 Control Register 2 (Timx_Cr2)
446
TIM6 Dma/Interrupt Enable Register (Timx_Dier)
446
TIM6 Status Register (Timx_Sr)
447
TIM6 Event Generation Register (Timx_Egr)
447
TIM6 Counter (Timx_Cnt)
447
TIM6 Prescaler (Timx_Psc)
448
TIM6 Auto-Reload Register (Timx_Arr)
448
TIM6 Register Map
449
Table 70. TIM6 Register Map and Reset Values
449
Low-Power Timer (LPTIM)
450
Introduction
450
LPTIM Main Features
450
LPTIM Implementation
450
Table 71. STM32F410 LPTIM Features
450
LPTIM Functional Description
451
LPTIM Block Diagram
451
LPTIM Trigger Mapping
451
Table 72. LPTIM1 External Trigger Connection
451
Figure 166. Low-Power Timer Block Diagram
451
LPTIM Input1 Multiplexing
452
LPTIM Reset and Clocks
452
Glitch Filter
452
Prescaler
453
Table 73. Prescaler Division Ratios
453
Figure 167. Glitch Filter Timing Diagram
453
Trigger Multiplexer
454
Operating Mode
454
Figure 168. LPTIM Output Waveform, Single Counting Mode Configuration
455
Figure 169. LPTIM Output Waveform, Single Counting Mode Configuration
455
Timeout Function
456
Waveform Generation
456
Figure 170. LPTIM Output Waveform, Continuous Counting Mode Configuration
456
Register Update
457
Figure 171. Waveform Generation
457
Counter Mode
458
Timer Enable
458
Encoder Mode
459
Table 74. Encoder Counting Scenarios
459
Debug Mode
460
LPTIM Low-Power Modes
460
Table 75. Effect of Low-Power Modes on the LPTIM
460
Figure 172. Encoder Mode Counting Sequence
460
LPTIM Interrupts
461
LPTIM Registers
461
LPTIM Interrupt and Status Register (LPTIM_ISR)
461
Table 76. Interrupt Events
461
LPTIM Interrupt Clear Register (LPTIM_ICR)
463
LPTIM Interrupt Enable Register (LPTIM_IER)
464
LPTIM Configuration Register (LPTIM_CFGR)
465
LPTIM Control Register (LPTIM_CR)
468
LPTIM Compare Register (LPTIM_CMP)
469
LPTIM Autoreload Register (LPTIM_ARR)
470
LPTIM Counter Register (LPTIM_CNT)
470
LPTIM1 Option Register (LPTIM1_OR)
471
LPTIM Register Map
472
Table 77. LPTIM Register Map and Reset Values
472
Window Watchdog (WWDG)
473
WWDG Introduction
473
WWDG Main Features
473
WWDG Functional Description
473
Figure 173. Watchdog Block Diagram
474
How to Program the Watchdog Timeout
475
Figure 174. Window Watchdog Timing Diagram
475
Debug Mode
476
WWDG Registers
477
Control Register (WWDG_CR)
477
Configuration Register (WWDG_CFR)
478
Status Register (WWDG_SR)
478
WWDG Register Map
479
Table 78. WWDG Register Map and Reset Values
479
Independent Watchdog (IWDG)
480
IWDG Introduction
480
IWDG Main Features
480
IWDG Functional Description
480
Hardware Watchdog
480
Register Access Protection
480
Debug Mode
481
Table 79. Min/Max IWDG Timeout Period at 32 Khz (LSI)
481
Figure 175. Independent Watchdog Block Diagram
481
IWDG Registers
482
Key Register (IWDG_KR)
482
Prescaler Register (IWDG_PR)
483
Reload Register (IWDG_RLR)
484
Status Register (IWDG_SR)
484
IWDG Register Map
485
Table 80. IWDG Register Map and Reset Values
485
Real-Time Clock (RTC)
486
Introduction
486
RTC Main Features
486
Figure 176. RTC Block Diagram
487
RTC Functional Description
488
Clock and Prescalers
488
Real-Time Clock and Calendar
488
Programmable Alarms
489
Periodic Auto-Wakeup
489
RTC Initialization and Configuration
490
Reading the Calendar
492
Resetting the RTC
493
RTC Synchronization
493
RTC Reference Clock Detection
494
RTC Coarse Digital Calibration
494
RTC Smooth Digital Calibration
495
Timestamp Function
497
Tamper Detection
498
Calibration Clock Output
499
Alarm Output
500
RTC and Low Power Modes
500
Table 81. Effect of Low Power Modes on RTC
500
RTC Interrupts
501
Table 82. Interrupt Control Bits
501
RTC Registers
502
RTC Time Register (RTC_TR)
502
RTC Date Register (RTC_DR)
503
RTC Control Register (RTC_CR)
504
RTC Initialization and Status Register (RTC_ISR)
506
RTC Prescaler Register (RTC_PRER)
508
RTC Wakeup Timer Register (RTC_WUTR)
509
RTC Calibration Register (RTC_CALIBR)
509
RTC Alarm a Register (RTC_ALRMAR)
511
RTC Alarm B Register (RTC_ALRMBR)
512
RTC Write Protection Register (RTC_WPR)
513
RTC Sub Second Register (RTC_SSR)
513
RTC Shift Control Register (RTC_SHIFTR)
514
RTC Time Stamp Time Register (RTC_TSTR)
515
RTC Time Stamp Date Register (RTC_TSDR)
515
RTC Timestamp Sub Second Register (RTC_TSSSR)
516
RTC Calibration Register (RTC_CALR)
516
RTC Tamper and Alternate Function Configuration Register
517
(Rtc_Tafcr)
517
RTC Alarm a Sub Second Register (RTC_ALRMASSR)
519
RTC Alarm B Sub Second Register (RTC_ALRMBSSR)
520
RTC Backup Registers (Rtc_Bkpxr)
521
RTC Register Map
522
Table 83. RTC Register Map and Reset Values
522
Fast-Mode Plus Inter-Integrated Circuit (FMPI2C) Interface
524
Introduction
524
FMPI2C Main Features
524
FMPI2C Implementation
525
FMPI2C Functional Description
525
Table 84. STM32F410 FMPI2C Implementation
525
Figure 177. FMPI2C Block Diagram
526
FMPI2C Block Diagram
526
FMPI2C Clock Requirements
527
FMPI2C Pins and Internal Signals
527
Table 85. FMPI2C Input/Output Pins
527
Table 86. FMPI2C Internal Input/Output Signals
527
Figure 178. I2C Bus Protocol
528
FMPI2C Initialization
528
Mode Selection
528
Table 87. Comparison of Analog Vs. Digital Filters
529
Figure 179. Setup and Hold Timings
530
Table 88. I2C-SMBUS Specification Data Setup and Hold Times
531
Figure 180. FMPI2C Initialization Flowchart
533
Software Reset
533
Data Transfer
534
Figure 181. Data Reception
534
Figure 182. Data Transmission
535
FMPI2C Slave Mode
536
Table 89. FMPI2C Configuration
536
Figure 183. Slave Initialization Flowchart
538
Figure 184. Transfer Sequence Flowchart for FMPI2C Slave Transmitter
540
Nostretch= 0
540
Figure 185. Transfer Sequence Flowchart for FMPI2C Slave Transmitter
541
Nostretch= 1
541
Figure 186. Transfer Bus Diagrams for FMPI2C Slave Transmitter
542
Figure 187. Transfer Sequence Flowchart for Slave Receiver with NOSTRETCH=0
543
Figure 188. Transfer Sequence Flowchart for Slave Receiver with NOSTRETCH=1
544
Figure 189. Transfer Bus Diagrams for FMPI2C Slave Receiver
544
FMPI2C Master Mode
545
Figure 190. Master Clock Generation
546
Table 90. I2C-SMBUS Specification Clock Timings
547
Figure 191. Master Initialization Flowchart
548
Figure 192. 10-Bit Address Read Access with HEAD10R=0
548
Figure 193. 10-Bit Address Read Access with HEAD10R=1
549
Figure 194. Transfer Sequence Flowchart for FMPI2C Master Transmitter for N≤255 Bytes
550
Figure 195. Transfer Sequence Flowchart for FMPI2C Master Transmitter for N>255 Bytes
551
Figure 196. Transfer Bus Diagrams for FMPI2C Master Transmitter
552
Figure 197. Transfer Sequence Flowchart for FMPI2C Master Receiver for N≤255 Bytes
554
Figure 198. Transfer Sequence Flowchart for FMPI2C Master Receiver for N >255 Bytes
555
Figure 199. Transfer Bus Diagrams for FMPI2C Master Receiver
556
FMPI2C_TIMINGR Register Configuration Examples
557
Table 91. Examples of Timing Settings for Fi2Cclk = 8 Mhz
557
Table 92. Examples of Timings Settings for Fi2Cclk = 16 Mhz
557
Smbus Specific Features
558
Figure 200. Timeout Intervals for T
560
Table 93. Smbus Timeout Specifications
560
Smbus Initialization
561
Table 94. SMBUS with PEC Configuration
562
Table 95. Examples of TIMEOUTA Settings for Various FMPI2CCLK Frequencies
562
Smbus Slave Mode
563
Smbus: FMPI2C_TIMEOUTR Register Configuration Examples
563
Table 97. Examples of TIMEOUTA Settings for Various FMPI2CCLK Frequencies
563
Figure 201. Transfer Sequence Flowchart for Smbus Slave Transmitter N Bytes + PEC
564
Figure 202. Transfer Bus Diagrams for Smbus Slave Transmitter (SBC=1)
565
Figure 203. Transfer Sequence Flowchart for Smbus Slave Receiver N Bytes + PEC
566
Figure 204. Bus Transfer Diagrams for Smbus Slave Receiver (SBC=1)
567
Figure 205. Bus Transfer Diagrams for Smbus Master Transmitter
568
Error Conditions
570
Figure 206. Bus Transfer Diagrams for Smbus Master Receiver
570
DMA Requests
572
Debug Mode
573
FMPI2C Low-Power Modes
573
Table 98. Effect of Low-Power Modes on the FMPI2C
573
FMPI2C Interrupts
574
Table 99. FMPI2C Interrupt Requests
574
FMPI2C Registers
575
FMPI2C Control Register 1 (FMPI2C_CR1)
575
FMPI2C Control Register 2 (FMPI2C_CR2)
578
FMPI2C Own Address 1 Register (FMPI2C_OAR1)
581
FMPI2C Own Address 2 Register (FMPI2C_OAR2)
582
FMPI2C Timing Register (FMPI2C_TIMINGR)
583
FMPI2C Timeout Register (FMPI2C_TIMEOUTR)
584
FMPI2C Interrupt and Status Register (FMPI2C_ISR)
585
FMPI2C Interrupt Clear Register (FMPI2C_ICR)
587
FMPI2C PEC Register (FMPI2C_PECR)
588
FMPI2C Receive Data Register (FMPI2C_RXDR)
589
FMPI2C Transmit Data Register (FMPI2C_TXDR)
589
FMPI2C Register Map
590
Table 100. FMPI2C Register Map and Reset Values
590
Inter-Integrated Circuit (I 2 C) Interface
592
I 2 C Introduction
592
I 2 C Main Features
593
C Functional Description
594
Mode Selection
594
Figure 207. I2C Bus Protocol
594
I2C Slave Mode
595
Figure 208. I2C Block Diagram
595
Figure 209. Transfer Sequence Diagram for Slave Transmitter
597
I2C Master Mode
598
Figure 210. Transfer Sequence Diagram for Slave Receiver
598
Figure 211. Transfer Sequence Diagram for Master Transmitter
601
Figure 212. Transfer Sequence Diagram for Master Receiver
603
Error Conditions
604
Programmable Noise Filter
605
Table 101. Maximum DNF[3:0] Value to be Compliant with Thd:dat(Max)
605
SDA/SCL Line Control
606
Smbus
606
Table 102. Smbus Vs. I2C
607
DMA Requests
609
Packet Error Checking
610
I 2 C Interrupts
611
Table 103. I2C Interrupt Requests
611
Figure 213. I2C Interrupt Mapping Diagram
612
I 2 C Debug Mode
613
I 2 C Registers
613
C Control Register 1 (I2C_CR1)
613
I 2 C Control Register 2 (I2C_CR2)
615
I 2 C Own Address Register 1 (I2C_OAR1)
617
I 2 C Own Address Register 2 (I2C_OAR2)
617
C Data Register (I2C_DR)
618
C Status Register 1 (I2C_SR1)
618
I 2 C Status Register 2 (I2C_SR2)
622
I 2 C Clock Control Register (I2C_CCR)
623
C TRISE Register (I2C_TRISE)
624
I 2 C FLTR Register (I2C_FLTR)
625
I2C Register Map
626
Table 104. I2C Register Map and Reset Values
626
Universal Synchronous Receiver Transmitter (USART) /Universal Asynchronous Receiver Transmitter (UART)
627
USART Introduction
627
USART Main Features
628
USART Implementation
629
USART Functional Description
629
Table 105. USART Features
629
Figure 214. USART Block Diagram
631
Figure 215. Word Length Programming
632
USART Character Description
632
Transmitter
633
Figure 216. Configurable Stop Bits
634
Figure 217. TC/TXE Behavior When Transmitting
635
Figure 218. Start Bit Detection When Oversampling by 16 or 8
636
Receiver
636
Figure 219. Data Sampling When Oversampling by 16
639
Figure 220. Data Sampling When Oversampling by 8
639
Table 106. Noise Detection from Sampled Data
639
Fractional Baud Rate Generation
641
Oversampling by 16
643
Table 107. Error Calculation for Programmed Baud Rates at F
643
Table 108. Error Calculation for Programmed Baud Rates at F
643
Oversampling by 8
645
Oversampling by 8
646
Oversampling by 16
647
Table 114. Error Calculation for Programmed Baud Rates at F
647
USART Receiver Tolerance to Clock Deviation
651
Multiprocessor Communication
652
Table 119. USART Receiver Tolerance When DIV Fraction Is 0
652
Table 120. USART Receiver Tolerance When Div_Fraction Is Different from 0
652
Figure 221. Mute Mode Using Idle Line Detection
653
Figure 222. Mute Mode Using Address Mark Detection
654
Parity Control
654
Table 121. Frame Formats
654
LIN (Local Interconnection Network) Mode
655
Figure 223. Break Detection in LIN Mode (11-Bit Break Length - LBDL Bit Is Set)
656
Figure 224. Break Detection in LIN Mode Vs. Framing Error Detection
657
USART Synchronous Mode
657
Figure 225. USART Example of Synchronous Transmission
658
Figure 226. USART Data Clock Timing Diagram (M=0)
658
Figure 227. USART Data Clock Timing Diagram (M=1)
659
Figure 228. RX Data Setup/Hold Time
659
Single-Wire Half-Duplex Communication
659
Figure 229. ISO 7816-3 Asynchronous Protocol
660
Smartcard
660
Figure 230. Parity Error Detection Using the 1.5 Stop Bits
661
Irda SIR ENDEC Block
662
Figure 231. Irda SIR ENDEC- Block Diagram
663
Figure 232. Irda Data Modulation (3/16) -Normal Mode
663
Continuous Communication Using DMA
664
Figure 233. Transmission Using DMA
665
Figure 234. Reception Using DMA
666
Figure 235. Hardware Flow Control between 2 Usarts
666
Hardware Flow Control
666
Figure 236. RTS Flow Control
667
Figure 237. CTS Flow Control
667
USART Interrupts
668
Table 122. USART Interrupt Requests
668
USART Registers
669
Status Register (USART_SR)
669
Figure 238. USART Interrupt Mapping Diagram
669
Data Register (USART_DR)
672
Baud Rate Register (USART_BRR)
672
Control Register 1 (USART_CR1)
673
Control Register 2 (USART_CR2)
675
Control Register 3 (USART_CR3)
676
Guard Time and Prescaler Register (USART_GTPR)
678
USART Register Map
679
Table 123. USART Register Map and Reset Values
679
Serial Peripheral Interface/ Inter-IC Sound (SPI/I2S)
680
Introduction
680
SPI Main Features
681
SPI Extended Features
682
I2S Features
682
SPI/I2S Implementation
682
Table 124. STM32F410 SPI Implementation
682
SPI Functional Description
683
General Description
683
Figure 239. SPI Block Diagram
683
Communications between One Master and One Slave
684
Figure 240. Full-Duplex Single Master/ Single Slave Application
684
Figure 241. Half-Duplex Single Master/ Single Slave Application
685
Figure 242. Simplex Single Master/Single Slave Application
686
Standard Multi-Slave Communication
687
Figure 243. Master and Three Independent Slaves
687
Multi-Master Communication
688
Slave Select (NSS) Pin Management
688
Figure 244. Multi-Master Application
688
Figure 245. Hardware/Software Slave Select Management
689
Communication Formats
690
Figure 246. Data Clock Timing Diagram
691
SPI Configuration
692
Procedure for Enabling SPI
692
Data Transmission and Reception Procedures
693
Figure 247. TXE/RXNE/BSY Behavior in Master / Full-Duplex Mode (BIDIMODE=0, RXONLY=0) in the Case of Continuous Transfers
694
Procedure for Disabling the SPI
695
Figure 248. TXE/RXNE/BSY Behavior in Slave / Full-Duplex Mode (BIDIMODE=0, RXONLY=0) in the Case of Continuous Transfers
695
Communication Using DMA (Direct Memory Addressing)
696
Figure 249. Transmission Using DMA
697
SPI Status Flags
698
Figure 250. Reception Using DMA
698
SPI Error Flags
699
SPI Special Features
700
TI Mode
700
CRC Calculation
701
Figure 251. TI Mode Transfer
701
SPI Interrupts
703
Table 125. SPI Interrupt Requests
703
S Functional Description
704
S General Description
704
Figure 252. I
704
I2S Full-Duplex
705
Supported Audio Protocols
706
Figure 253. Full-Duplex Communication
706
Figure 254. I 2 S Philips Protocol Waveforms (16/32-Bit Full Accuracy, CPOL = 0)
707
Figure 255. I 2 S Philips Standard Waveforms (24-Bit Frame with CPOL = 0)
707
Figure 256. Transmitting 0X8Eaa33
708
Figure 257. Receiving 0X8Eaa33
708
Figure 258. I
708
Figure 259. Example of 16-Bit Data Frame Extended to 32-Bit Channel Frame
709
Figure 260. MSB Justified 16-Bit or 32-Bit Full-Accuracy Length with CPOL = 0
709
Figure 261. MSB Justified 24-Bit Frame Length with CPOL = 0
709
Figure 262. MSB Justified 16-Bit Extended to 32-Bit Packet Frame with CPOL = 0
710
Figure 263. LSB Justified 16-Bit or 32-Bit Full-Accuracy with CPOL = 0
710
Figure 264. LSB Justified 24-Bit Frame Length with CPOL = 0
710
Figure 265. Operations Required to Transmit 0X3478Ae
711
Figure 266. Operations Required to Receive 0X3478Ae
711
Figure 267. LSB Justified 16-Bit Extended to 32-Bit Packet Frame with CPOL = 0
711
Figure 268. Example of 16-Bit Data Frame Extended to 32-Bit Channel Frame
712
Figure 269. PCM Standard Waveforms (16-Bit)
712
Figure 270. PCM Standard Waveforms (16-Bit Extended to 32-Bit Packet Frame)
712
Clock Generator
713
Figure 271. Audio Sampling Frequency Definition
713
Figure 272. I
713
Table 126. Audio-Frequency Precision Using Standard 8 Mhz HSE
714
I 2 S Master Mode
715
I 2 S Slave Mode
717
I 2 S Status Flags
718
I 2 S Error Flags
719
I 2 S Interrupts
720
DMA Features
720
Table 127. I
720
SPI and I 2 S Registers
721
SPI Control Register 1 (SPI_CR1) (Not Used in I 2 S Mode)
721
SPI Control Register 2 (SPI_CR2)
723
SPI Status Register (SPI_SR)
724
SPI Data Register (SPI_DR)
726
SPI CRC Polynomial Register (SPI_CRCPR) (Not Used in I
726
Mode
726
SPI RX CRC Register (SPI_RXCRCR) (Not Used in I 2 S Mode)
727
SPI TX CRC Register (SPI_TXCRCR) (Not Used in I 2 S Mode)
727
SPI_I 2 S Configuration Register (SPI_I2SCFGR)
728
SPI_I 2 S Prescaler Register (SPI_I2SPR)
729
SPI Register Map
731
Table 128. SPI Register Map and Reset Values
731
Debug Support (DBG)
732
Overview
732
Figure 273. Block Diagram of STM32 MCU and Cortex ® -M4 with FPU-Level
732
Reference Arm® Documentation
733
SWJ Debug Port (Serial Wire and JTAG)
733
Mechanism to Select the JTAG-DP or the SW-DP
734
Pinout and Debug Port Pins
734
Figure 274. SWJ Debug Port
734
Flexible SWJ-DP Pin Assignment
735
SWJ Debug Port Pins
735
Table 129. SWJ Debug Port Pins
735
Table 130. Flexible SWJ-DP Pin Assignment
735
Internal Pull-Up and Pull-Down on JTAG Pins
736
Using Serial Wire and Releasing the Unused Debug Pins as Gpios
737
JTAG TAP Connection
737
Figure 275. JTAG TAP Connections
738
ID Codes and Locking Mechanism
739
MCU Device ID Code
739
Boundary Scan TAP
739
Cortex ® -M4 with FPU TAP
739
Cortex ® -M4 with FPU JEDEC-106 ID Code
740
JTAG Debug Port
740
Table 131. JTAG Debug Port Data Registers
740
Table 132. 32-Bit Debug Port Registers Addressed through the Shifted Value A[3:2]
741
SW Debug Port
742
SW Protocol Introduction
742
SW Protocol Sequence
742
Table 133. Packet Request (8-Bits)
742
SW-DP State Machine (Reset, Idle States, ID Code)
743
DP and AP Read/Write Accesses
743
Table 134. ACK Response (3 Bits)
743
Table 135. DATA Transfer (33 Bits)
743
SW-DP Registers
744
Table 136. SW-DP Registers
744
SW-AP Registers
745
AHB-AP (AHB Access Port) - Valid for both JTAG-DP and SW-DP
745
Table 137. Cortex -M4 with FPU AHB-AP Registers
745
Core Debug
746
Table 138. Core Debug Registers
746
Capability of the Debugger Host to Connect under System Reset
747
FPB (Flash Patch Breakpoint)
747
DWT (Data Watchpoint Trigger)
748
ITM (Instrumentation Trace Macrocell)
748
General Description
748
Time Stamp Packets, Synchronization and Overflow Packets
748
Table 139. Main ITM Registers
749
ETM (Embedded Trace Macrocell)
750
General Description
750
Signal Protocol, Packet Types
750
Main ETM Registers
750
Configuration Example
751
MCU Debug Component (DBGMCU)
751
Debug Support for Low-Power Modes
751
Table 140. Main ETM Registers
751
Debug Support for Timers, Watchdog, and I C
752
Debug MCU Configuration Register
752
Debug MCU APB1 Freeze Register (DBGMCU_APB1_FZ)
753
Debug MCU APB2 Freeze Register (DBGMCU_APB2_FZ)
755
TPIU (Trace Port Interface Unit)
756
Introduction
756
Figure 276. TPIU Block Diagram
756
TRACE Pin Assignment
757
Table 141. Asynchronous TRACE Pin Assignment
757
Table 142. Synchronous TRACE Pin Assignment
757
TPUI Formatter
758
Table 143. Flexible TRACE Pin Assignment
758
TPUI Frame Synchronization Packets
759
Transmission of the Synchronization Frame Packet
759
Synchronous Mode
759
Asynchronous Mode
760
TRACECLKIN Connection
760
TPIU Registers
760
Table 144. Important TPIU Registers
760
26.17.10 Example of Configuration
761
DBG Register Map
762
Table 145. DBG Register Map and Reset Values
762
Device Electronic Signature
763
Unique Device ID Register (96 Bits)
763
Flash Size
764
Package Data Register
764
Revision History
765
Table 146. Document Revision History
765
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ST STM32F410 Specifications
General
Brand
ST
Model
STM32F410
Category
Microcontrollers
Language
English
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