Power controller (PWR) RM0401
80/771 RM0401 Rev 3
When the code is executed from internal SRAM and the Flash memory is configured in low-
power mode before entering Stop mode, the Flash memory stays in low-power mode after
waking up from Stop. In this case, only the HSI RC clock startup time and the regulator
wakeup time apply.
Entering Stop mode
The Stop mode is entered according to Section : Entering low-power mode, when the
SLEEPDEEP bit in the Cortex
®
-M4 with FPU System Control register is set.
Refer to Table 20 for details on how to enter the Stop mode.
To further reduce power consumption in Stop mode, the internal voltage regulator can be put
in low-power mode. This is configured by the LPDS bit of the
PWR power control register
(PWR_CR).
If Flash memory programming is ongoing, the Stop mode entry is delayed until the memory
access is finished.
If an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB
access is finished.
The following features can be selected by programming individual control bits before
entering Stop mode:
• Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a Reset. See
Table 19. Stop operating modes
Stop mode MRLV bit LPLV bit FPDS bit LPDS bit Wakeup latency
STOP MR 0 - 0 0 HSI RC startup time
STOP MRFPD 0 - 1 0
HSI RC startup time +
Flash wakeup time from Deep Power
Down mode
STOP LP0001
HSI RC startup time +
regulator wakeup time from LP mode
STOP LPFPD - 0 1 1
HSI RC startup time +
Flash wakeup time from Deep Power
Down mode +
regulator wakeup time from LP mode
STOP MRLV 1 - - 0
HSI RC startup time +
Flash wakeup time from Deep Power
Down mode +
Main regulator from low voltage mode
STOP LPLV-1-1
HSI RC startup time +
Flash wakeup time from Deep Power
Down mode +
regulator wakeup time from Low
Voltage LP mode
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