ST STM32F410 User Manual

RM0401 Rev 3 117/771
RM0401 Reset and clock control (RCC)
134
5.3.9 RCC APB1 peripheral clock enable register (RCC_APB1ENR)
Address offset: 0x40
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
Bit 0 GPIOAEN: IO port A clock enable
Set and cleared by software.
0: IO port A clock disabled
1: IO port A clock enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res.
DAC
EN
PWR
EN
Res. Res. Res.
I2C4
EN
Res.
I2C2
EN
I2C1
EN
Res. Res. Res.
USART2
EN
Res.
rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3
EN
SPI2
EN
Res. Res.
WWDG
EN
RTCAPB
EN
LPTIM1
EN
Res. Res. Res. Res.
TIM6
EN
TIM5
EN
Res. Res. Res.
rw rw rw rw rw rw rw
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 DACEB: DAC interface clock enable
Set and cleared by software.
0: DAC interface clock disabled
1: DAC interface clock enable
Bit 28 PWREN: Power interface clock enable
Set and cleared by software.
0: Power interface clock disabled
1: Power interface clock enable
Bits 27:25 Reserved, must be kept at reset value.
Bit 24 I2C4EN: I2C4 clock enable
Set and cleared by software.
0: I2C4 clock disabled
1: I2C4 clock enabled
Bit 23 Reserved, must be kept at reset value.
Bit 22 I2C2EN: I2C2 clock enable
Set and cleared by software.
0: I2C2 clock disabled
1: I2C2 clock enabled
Bit 21 I2C1EN: I2C1 clock enable
Set and cleared by software.
0: I2C1 clock disabled
1: I2C1 clock enabled
Bits 20:18 Reserved, must be kept at reset value.

ST STM32F410 Specifications

General

Brand	ST
Model	STM32F410
Category	Microcontrollers
Language	English