ST STM32F410

System and memory overview RM0401
36/771 RM0401 Rev 3
2 System and memory overview
2.1 System architecture
In STM32F410, the main system consists of 32-bit multilayer AHB bus matrix that
interconnects:
• Six masters:
–Cortex
®
-M4 with FPU core I-bus, D-bus and S-bus
– DMA1 memory bus
– DMA2 memory bus
– DMA2 peripheral bus
• Five slaves:
– Internal Flash memory ICode bus
– Internal Flash memory DCode bus
– Main internal SRAM
– AHB1 peripherals including AHB to APB bridges and APB peripherals
– AHB2 peripherals
The bus matrix provides access from a master to a slave, enabling concurrent access and
efficient operation even when several high-speed peripherals work simultaneously. This
architecture is shown in
Figure 1.
Figure 1. System architecture
1. The Flash memory size is 512 Kbytes or 128 Mbytes while SRAM1 size is 256 Kbytes.
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