RM0401 Rev 3 121/771
RM0401 Reset and clock control (RCC)
134
5.3.11 RCC AHB1 peripheral clock enable in low power mode register
(RCC_AHB1LPENR)
Address offset: 0x50
Reset value: 0x0061 900F
Access: no wait state, word, half-word and byte access.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RNG
LPEN
Res. Res. Res. Res. Res. Res. Res. Res.
DMA2
LPEN
DMA1
LPEN
Res. Res. Res. Res.
SRAM1
LPEN
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLITF
LPEN
Res. Res.
CRC
LPEN
Res. Res. Res. Res.
GPIOH
LPEN
Res. Res. Res. Res.
GPIOC
LPEN
GPIOB
LPEN
GPIOA
LPEN
rw rw rw rw rw rw
Bit 31 RNGPEN: RNG clock enable during Sleep mode
Set and cleared by software.
0: RNG clock disabled during Sleep mode
1: RNG clock enabled during Sleep mode
Bits 30:23 Reserved, must be kept at reset value.
Bit 22 DMA2LPEN: DMA2 clock enable during Sleep mode
Set and cleared by software.
0: DMA2 clock disabled during Sleep mode
1: DMA2 clock enabled during Sleep mode
Bit 21 DMA1LPEN: DMA1 clock enable during Sleep mode
Set and cleared by software.
0: DMA1 clock disabled during Sleep mode
1: DMA1 clock enabled during Sleep mode
Bits 20:17 Reserved, must be kept at reset value.
Bit 16 SRAM1LPEN: SRAM1interface clock enable during Sleep mode
Set and cleared by software.
0: SRAM1 interface clock disabled during Sleep mode
1: SRAM1 interface clock enabled during Sleep mode
Bit 15 FLITFLPEN: Flash interface clock enable during Sleep mode
Set and cleared by software.
0: Flash interface clock disabled during Sleep mode
1: Flash interface clock enabled during Sleep mode
Bits 14:13 Reserved, must be kept at reset value.
Bit 12 CRCLPEN: CRC clock enable during Sleep mode
Set and cleared by software.
0: CRC clock disabled during Sleep mode
1: CRC clock enabled during Sleep mode
Bits 11:8 Reserved, must be kept at reset value.
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