Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401
526/771 RM0401 Rev 3
22.4.1 FMPI2C block diagram
The block diagram of the FMPI2C interface is shown in Figure 177.
Figure 177. FMPI2C block diagram
The FMPI2C is clocked by an independent clock source which allows to the FMPI2C to
operate independently from the PCLK frequency.
For I2C I/Os supporting 20 mA output current drive for Fast-mode Plus operation, the driving
capability is enabled through control bits in the system configuration controller (SYSCFG).
Refer to Section 22.3: FMPI2C implementation.
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