RM0401 Rev 3 45/771
RM0401 Embedded Flash memory interface
68
3 Embedded Flash memory interface
3.1 Introduction
The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash
memory. It implements the erase and program Flash memory operations and the read and
write protection mechanisms.
The Flash memory interface accelerates code execution with a system of instruction
prefetch and cache lines.
3.2 Main features
• Flash memory read operations
• Flash memory program/erase operations
• Read / write protections
• Prefetch on I-Code
• 64 cache lines of 128 bits on I-Code
• 8 cache lines of 128 bits on D-Code
Figure 3 shows the Flash memory interface connection inside the system architecture.
Figure 3. Flash memory interface connection inside system architecture
&RUWH[
FRUH
'0$
'0$
'FRGHEXV
,&RGHEXV
&RUWH[0ZLWK)38
,&RGH
'&RGH
6EXV
$+%
SHULSK
)ODVK
PHPRU\
)ODVKLQWHUIDFH
65$0DQG
([WHUQDO
PHPRULHV
$+%
SHULSK
)/,7)UHJLVWHUV
$+%
ELW
LQVWUXFWLRQ
EXV
$FFHVVWRLQVWUXFWLRQLQ)ODVKPHPRU\
$FFHVVWRGDWDDQGOLWHUDOSRROLQ)ODVKPHPRU\
)/,7)UHJLVWHUDFFHVV
069
$+%
ELW
GDWDEXV
$+%
ELW
V\VWHPEXV
)ODVK
PHPRU\
EXV
ELWV
To Next Page
Loading...
Need help?
General
