Power controller (PWR) RM0401
82/771 RM0401 Rev 3
4.3.8 Standby mode
The Standby mode allows to achieve the lowest power consumption. It is based on the
Cortex
®
-M4 with FPU deepsleep mode, with the voltage regulator disabled. The 1.2 V
domain is consequently powered off. The PLLs, the HSI oscillator and the HSE oscillator are
also switched off. SRAM and register contents are lost except for registers in the backup
domain (RTC registers and RTC backup register), and Standby circuitry (see
Figure 7).
Entering Standby mode
The Standby mode is entered according to Section : Entering low-power mode, when the
SLEEPDEEP bit in the Cortex
®
-M4 with FPU System Control register is set.
Refer to Table 21 for more details on how to enter Standby mode.
In Standby mode, the following features can be selected by programming individual control
bits:
• Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a reset. See
Section 20.3 in Section 20: Independent watchdog (IWDG).
• Real-time clock (RTC): this is configured by the RTCEN bit in the backup domain
control register (RCC_BDCR)
• Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status
register (RCC_CSR).
• External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
backup domain control register (RCC_BDCR)
Exiting Standby mode
The Standby mode is exited according to Section : Exiting low-power mode. The SBF status
flag in PWR_CR (see Section 4.4.2: PWR power control/status register (PWR_CSR))
indicates that the MCU was in Standby mode. All registers are reset after wakeup from
Standby except for PWR_CR.
Refer to Table 21 for more details on how to exit Standby mode.
Mode exit
If WFI or Return from ISR was used for entry:
Any EXTI lines configured in Interrupt mode (the corresponding EXTI
Interrupt vector must be enabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wakeup capability. Refer to
Table 39: Vector table.
If WFE was used for entry and SEVONPEND = 0
Any EXTI lines configured in event mode. Refer to Section 9.2.3:
Wakeup event management.
If WFE was used for entry and SEVONPEND = 1:
– Any EXTI lines configured in Interrupt mode (even if the corresponding
EXTI Interrupt vector is disabled in the NVIC). The interrupt source can
be an external interrupt or a peripheral with wakeup capability. Refer to v.
– Wakeup event: refer to Section 9.2.3: Wakeup event management.
Wakeup latency Refer to Table 19: Stop operating modes
Table 20. Stop mode entry and exit (continued)
Stop mode Description
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