Debug support (DBG) RM0401
740/771 RM0401 Rev 3
26.6.4 Cortex
®
-M4 with FPU JEDEC-106 ID code
The Arm
®
Cortex
®
-M4 with FPU integrates a JEDEC-106 ID code. It is located in the 4KB
ROM table mapped on the internal PPB bus at address 0xE00F FFD0_0xE00F FFE0.
This code is accessible by the JTAG Debug Port (4 to 5 pins) or by the SW Debug Port (two
pins) or by the user software.
26.7 JTAG debug port
A standard JTAG state machine is implemented with a 4-bit instruction register (IR) and five
data registers (for full details, refer to the Cortex
®
-M4 with FPUr0p1 Technical Reference
Manual (TRM), for references, please see Section 26.2: Reference Arm® documentation).
Table 131. JTAG debug port data registers
IR(3:0) Data register Details
1111
BYPASS
[1 bit]
1110
IDCODE
[32 bits]
ID CODE
0x4BA0 0477 (Arm
®
Cortex
®
-M4 with FPU r0p1 ID Code)
1010
DPACC
[35 bits]
Debug port access register
This initiates a debug port and allows access to a debug port register.
– When transferring data IN:
Bits 34:3 = DATA[31:0] = 32-bit data to transfer for a write request
Bits 2:1 = A[3:2] = 2-bit address of a debug port register.
Bit 0 = RnW = Read request (1) or write request (0).
– When transferring data OUT:
Bits 34:3 = DATA[31:0] = 32-bit data which is read following a read
request
Bits 2:0 = ACK[2:0] = 3-bit Acknowledge:
010 = OK/FAULT
001 = WAIT
OTHER = reserved
Refer to Table 132 for a description of the A[3:2] bits
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