RM0401 Rev 3 125/771
RM0401 Reset and clock control (RCC)
134
5.3.13 RCC APB2 peripheral clock enabled in low power mode register
(RCC_APB2LPENR)
Address offset: 0x64
Reset value: 0x0007 7930
Access: no wait state, word, half-word and byte access.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
SPI5
LPEN
Res.
TIM11
LPEN
Res.
TIM9
LPEN
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI
LPEN
SYSC
FG
LPEN
Res.
SPI1
LPEN
Res. Res. Res.
ADC1
LPEN
Res. Res.
USART6
LPEN
USART1
LPEN
Res. Res. Res.
TIM1
LPEN
rw rw rw rw rw rw rw
Bits 31:21 Reserved, must be kept at reset value.
Bit 20 SPI5LPEN: SPI5 clock enable during Sleep mode
This bit is set and cleared by software
0: SPI5 clock disabled during Sleep mode
1: SPI5 clock enabled during Sleep mode
Bit 19 Reserved, must be kept at reset value.
Bit 18 TIM11LPEN: TIM11 clock enable during Sleep mode
Set and cleared by software.
0: TIM11 clock disabled during Sleep mode
1: TIM11 clock enabled during Sleep mode
Bit 17 Reserved, must be kept at reset value.
Bit 16 TIM9LPEN: TIM9 clock enable during sleep mode
Set and cleared by software.
0: TIM9 clock disabled during Sleep mode
1: TIM9 clock enabled during Sleep mode
Bit 15 EXTILPEN: System controller and external interrupt clock enable during sleep mode
Set and cleared by software.
0: EXTI clock disabled during Sleep mode
1: EXTI clock enabled during Sleep mode
Bit 14 SYSCFGLPEN: System configuration controller clock enable during Sleep mode
Set and cleared by software.
0: System configuration controller clock disabled during Sleep mode
1: System configuration controller clock enabled during Sleep mode
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1LPEN: SPI1 clock enable during Sleep mode
Set and cleared by software.
0: SPI1 clock disabled during Sleep mode
1: SPI1 clock enabled during Sleep mode
Bits 11:9 Reserved, must be kept at reset value.
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