RM0401 Rev 3 461/771
RM0401 Low-power timer (LPTIM)
472
18.6 LPTIM interrupts
The following events generate an interrupt/wake-up event, if they are enabled through the
LPTIM_IER register:
• Compare match
• Auto-reload match (whatever the direction if encoder mode)
• External trigger event
• Autoreload register write completed
• Compare register write completed
• Direction change (encoder mode), programmable (up / down / both).
Note: If any bit in the LPTIM_IER register (Interrupt Enable Register) is set after that its
corresponding flag in the LPTIM_ISR register (Status Register) is set, the interrupt is not
asserted.
18.7 LPTIM registers
18.7.1 LPTIM interrupt and status register (LPTIM_ISR)
Address offset: 0x000
Reset value: 0x0000 0000
Table 76. Interrupt events
Interrupt event Description
Compare match
Interrupt flag is raised when the content of the Counter register
(LPTIM_CNT) matches the content of the compare register (LPTIM_CMP).
Auto-reload match
Interrupt flag is raised when the content of the Counter register
(LPTIM_CNT) matches the content of the Auto-reload register
(LPTIM_ARR).
External trigger event Interrupt flag is raised when an external trigger event is detected
Auto-reload register
update OK
Interrupt flag is raised when the write operation to the LPTIM_ARR register
is complete.
Compare register
update OK
Interrupt flag is raised when the write operation to the LPTIM_CMP register
is complete.
Direction change
Used in Encoder mode. Two interrupt flags are embedded to signal
direction change:
– UP flag signals up-counting direction change
– DOWN flag signals down-counting direction change.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. DOWN UP
ARRO
K
CMP
OK
EXTTR
IG
ARRM CMPM
rrrrrrr