ST STM32F410 User Manual

RM0401 Rev 3 119/771
RM0401 Reset and clock control (RCC)
134
5.3.10 RCC APB2 peripheral clock enable register
(RCC_APB2ENR)
Address offset: 0x44
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SPI5EN Res.
TIM11
EN
Res.
TIM9
EN
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTIEN
SYSCF
G EN
Res.
SPI1
EN
Res. Res. Res.
ADC1
EN
Res. Res.
USART6
EN
USART1
EN
Res. Res. Res.
TIM1
EN
rw rw rw rw rw rw rw
Bits 31:21 Reserved, must be kept at reset value.
Bit 20 SPI5EN:SPI5 clock enable
This bit is set and cleared by software
0: SPI5 clock disabled
1: SPI5 clock enabled
Bit 19 Reserved, must be kept at reset value.
Bit 18 TIM11EN: TIM11 clock enable
Set and cleared by software.
0: TIM11 clock disabled
1: TIM11 clock enabled
Bit 17 Reserved, must be kept at reset value.
Bit 16 TIM9EN: TIM9 clock enable
Set and cleared by software.
0: TIM9 clock disabled
1: TIM9 clock enabled
Bit 16 EXTIEN: System controller and external interrupt clock enable
Set and cleared by software.
0: EXTI clock disabled
1: EXTI clock enabled
Bit 14 SYSCFGEN: System configuration controller clock enable
Set and cleared by software.
0: System configuration controller clock disabled
1: System configuration controller clock enabled
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1EN: SPI1 clock enable
Set and cleared by software.
0: SPI1 clock disabled
1: SPI1 clock enabled
Bits 11:9 Reserved, must be kept at reset value.

ST STM32F410 Specifications

General

Brand	ST
Model	STM32F410
Category	Microcontrollers
Language	English