System configuration controller (SYSCFG) RM0401
160/771 RM0401 Rev 3
7.2.9 Compensation cell control register (SYSCFG_CFGR)
Address offset: 0x2C
Reset value: 0x0000 0000
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 READY: Compensation cell ready flag
0: I/O compensation cell not ready
1: O compensation cell ready
Bits 7:2 Reserved, must be kept at reset value.
Bit 0 CMP_PD: Compensation cell power-down
0: I/O compensation cell power-down mode
1: I/O compensation cell enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109 8 7 65432 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
FMPI2C4
_SDA
FMPI2C4_
SCL
rw
rw
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 FMPI2C4_SDA
Set and cleared by software. When this bit is set, it forces FM+ drive capability on
FMPI2C4_SDA pin selected through GPIO port mode register and GPIO alternate
function selection bits.
Bit 0 FMPI2C4_SCL
Set and cleared by software. When this bit is set, it forces FM+ drive capability on
FMPI2C4_SCL pin selected through GPIO port mode register and GPIO alternate
function selection bits.
To Next Page
Loading...
Need help?
General
