To Next Page

To Previous Page

General-purpose I/Os (GPIO) RM0401

154/771 RM0401 Rev 3

Refer to Section 2.2 on page 41 for the register boundary addresses.

0x1C

GPIOx_LCKR

(where x =A..C

and H)

Res.

LCKK

LCK15

LCK14

LCK13

LCK12

LCK11

LCK10

LCK9

LCK8

LCK7

LCK6

LCK5

LCK4

LCK3

LCK2

LCK1

LCK0

Reset value 00000000000000000

0x20

GPIOx_AFRL

(where x =A..C

and H)

AFRL7[3:0] AFRL6[3:0] AFRL5[3:0] AFRL4[3:0] AFRL3[3:0] AFRL2[3:0] AFRL1[3:0] AFRL0[3:0]

Reset value 00000000000000000000000000000000

0x24

GPIOx_AFRH

(where x =A..C

and H)

AFRH15[3:0] AFRH14[3:0] AFRH13[3:0] AFRH12[3:0] AFRH11[3:0] AFRH10[3:0] AFRH9[3:0] AFRH8[3:0]

Reset value 00000000000000000000000000000000

Table 27. GPIO register map and reset values (continued)

Offset Register

Default Chapter2
- Table of Contents2
- SYSCFG External Interrupt Configuration Register4
Documentation Conventions34
- General Information34
- List of Abbreviations for Registers34
- Glossary35
- Availability of Peripherals35
System and Memory Overview36
- System Architecture36
- Memory Organization38
- Embedded SRAM41
- Flash Memory Overview41
- Bit Banding42
- Boot Configuration43
- Table 2. Boot Modes43
- Table 3. Embedded Bootloader Interfaces43
- Table 4. Memory Mapping Vs. Boot Mode/Physical Remap in STM32F41044
Embedded Flash Memory Interface45
- Introduction45
- Main Features45
- Figure 3. Flash Memory Interface Connection Inside System Architecture45
- Embedded Flash Memory46
- Table 5. Flash Module Organization46
- Read Interface47
- Erase and Program Operations50
- Option Bytes53
- One-Time Programmable Bytes60
- Table 12. OTP Area Organization60
- Flash Interface Registers61
Power Controller (PWR)69
- Power Supplies69
- Power Supply Supervisor72
- Low-Power Modes74
- Power Control Registers86
  - PWR Power Control Register (PWR_CR)86
  - PWR Power Control/Status Register (PWR_CSR)88
- PWR Register Map90
- Table 22. PWR - Register Map and Reset Values90
Reset and Clock Control (RCC)91
- Reset91
- Clocks93
- RCC Registers102
General-Purpose I/Os (GPIO)135
- GPIO Introduction135
- GPIO Main Features135
- GPIO Functional Description135
- GPIO Registers147
System Configuration Controller (SYSCFG)155
- I/O Compensation Cell155
- SYSCFG Registers155
Direct Memory Access Controller (DMA)162
- DMA Introduction162
- DMA Main Features162
- DMA Functional Description164
- DMA Interrupts183
- Table 37. DMA Interrupt Requests183
- DMA Registers184
Interrupts and Events198
- Nested Vectored Interrupt Controller (NVIC)198
- External Interrupt/Event Controller (EXTI)198
- EXTI Registers206
CRC Calculation Unit211
- CRC Introduction211
- CRC Main Features211
- CRC Functional Description211
- Figure 31. CRC Calculation Unit Block Diagram211
- CRC Registers212
Analog-To-Digital Converter (ADC)215
- ADC Introduction215
- ADC Main Features215
- ADC Functional Description215
Digital-To-Analog Converter (DAC)243
- Introduction243
- DAC Main Features243
- DAC Output Buffer Enable244
- Table 51. DAC Pins244
- Figure 40. DAC Channel Block Diagram244
- DAC Channel Enable245
- Single Mode Functional Description245
- Noise Generation248
- Figure 43. DAC LFSR Register Calculation Algorithm248
- Figure 44. DAC Conversion (SW Trigger Enabled) with LFSR Wave Generation248
- Triangle-Wave Generation249
- Figure 45. DAC Triangle Wave Generation249
- Figure 46. DAC Conversion (SW Trigger Enabled) with Triangle Wave Generation249
- DMA Request250
- DAC Registers251
True Random Number Generator (RNG)257
- Introduction257
- RNG Main Features257
- RNG Functional Description258
- RNG Low-Power Usage263
- RNG Interrupts263
- RNG Processing Time263
- Table 55. RNG Interrupt Requests263
- Entropy Source Validation264
  - Introduction264
  - Validation Conditions264
- RNG Registers265
Advanced-Control Timers (TIM1)269
- TIM1 Introduction269
- TIM1 Main Features269
- Figure 49. Advanced-Control Timer Block Diagram270
- TIM1 Functional Description271
- TIM1 Registers313
- With Break Feature330
General-Purpose Timers (TIM5)340
- TIM5 Introduction340
- TIM5 Main Features340
- TIM5 Functional Description341
- TIM5 Registers369
General-Purpose Timers (TIM9 and TIM11)390
- TIM9 and TIM11 Introduction390
- TIM9 and TIM11 Main Features390
- TIM9 and TIM11 Functional Description393
- TIM9 Registers411
- TIM11 Registers426
Basic Timers (TIM6)437
- Introduction437
- TIM6 Main Features437
- Figure 156. Basic Timer Block Diagram437
- TIM6 Functional Description438
- TIM6 Registers445
Low-Power Timer (LPTIM)450
- Introduction450
- LPTIM Main Features450
- LPTIM Implementation450
- Table 71. STM32F410 LPTIM Features450
- LPTIM Functional Description451
- LPTIM Low-Power Modes460
- Table 75. Effect of Low-Power Modes on the LPTIM460
- Figure 172. Encoder Mode Counting Sequence460
- LPTIM Interrupts461
- LPTIM Registers461
Window Watchdog (WWDG)473
- WWDG Introduction473
- WWDG Main Features473
- WWDG Functional Description473
- Figure 173. Watchdog Block Diagram474
- How to Program the Watchdog Timeout475
- Figure 174. Window Watchdog Timing Diagram475
- Debug Mode476
- WWDG Registers477
Independent Watchdog (IWDG)480
- IWDG Introduction480
- IWDG Main Features480
- IWDG Functional Description480
- IWDG Registers482
Real-Time Clock (RTC)486
- Introduction486
- RTC Main Features486
- Figure 176. RTC Block Diagram487
- RTC Functional Description488
- RTC and Low Power Modes500
- Table 81. Effect of Low Power Modes on RTC500
- RTC Interrupts501
- Table 82. Interrupt Control Bits501
- RTC Registers502
Fast-Mode Plus Inter-Integrated Circuit (FMPI2C) Interface524
- Introduction524
- FMPI2C Main Features524
- FMPI2C Implementation525
- FMPI2C Functional Description525
- FMPI2C Low-Power Modes573
- Table 98. Effect of Low-Power Modes on the FMPI2C573
- FMPI2C Interrupts574
- Table 99. FMPI2C Interrupt Requests574
- FMPI2C Registers575
Inter-Integrated Circuit (I 2 C) Interface592
- I 2 C Introduction592
- I 2 C Main Features593
- C Functional Description594
- I 2 C Interrupts611
- Table 103. I2C Interrupt Requests611
- Figure 213. I2C Interrupt Mapping Diagram612
- I 2 C Debug Mode613
- I 2 C Registers613
Universal Synchronous Receiver Transmitter (USART) /Universal Asynchronous Receiver Transmitter (UART)627
- USART Introduction627
- USART Main Features628
- USART Implementation629
- USART Functional Description629
- USART Interrupts668
- Table 122. USART Interrupt Requests668
- USART Registers669
Serial Peripheral Interface/ Inter-IC Sound (SPI/I2S)680
- Introduction680
- SPI/I2S Implementation682
- Table 124. STM32F410 SPI Implementation682
- SPI Functional Description683
- SPI Special Features700
- SPI Interrupts703
- Table 125. SPI Interrupt Requests703
- S Functional Description704
- SPI and I 2 S Registers721
Debug Support (DBG)732
- Overview732
- Figure 273. Block Diagram of STM32 MCU and Cortex ® -M4 with FPU-Level732
- Reference Arm® Documentation733
- SWJ Debug Port (Serial Wire and JTAG)733
  - Mechanism to Select the JTAG-DP or the SW-DP734
- Pinout and Debug Port Pins734
  - Figure 274. SWJ Debug Port734
  - Flexible SWJ-DP Pin Assignment735
  - SWJ Debug Port Pins735
  - Table 129. SWJ Debug Port Pins735
  - Table 130. Flexible SWJ-DP Pin Assignment735
  - Internal Pull-Up and Pull-Down on JTAG Pins736
  - Using Serial Wire and Releasing the Unused Debug Pins as Gpios737
- JTAG TAP Connection737
- Figure 275. JTAG TAP Connections738
- ID Codes and Locking Mechanism739
  - MCU Device ID Code739
  - Boundary Scan TAP739
  - Cortex ® -M4 with FPU TAP739
  - Cortex ® -M4 with FPU JEDEC-106 ID Code740
- JTAG Debug Port740
- Table 131. JTAG Debug Port Data Registers740
- Table 132. 32-Bit Debug Port Registers Addressed through the Shifted Value A[3:2]741
- SW Debug Port742
  - SW Protocol Introduction742
  - SW Protocol Sequence742
  - Table 133. Packet Request (8-Bits)742
  - SW-DP State Machine (Reset, Idle States, ID Code)743
  - DP and AP Read/Write Accesses743
  - Table 134. ACK Response (3 Bits)743
  - Table 135. DATA Transfer (33 Bits)743
  - SW-DP Registers744
  - Table 136. SW-DP Registers744
  - SW-AP Registers745
- AHB-AP (AHB Access Port) - Valid for both JTAG-DP and SW-DP745
- Table 137. Cortex -M4 with FPU AHB-AP Registers745
- Core Debug746
- Table 138. Core Debug Registers746
- Capability of the Debugger Host to Connect under System Reset747
- FPB (Flash Patch Breakpoint)747
- DWT (Data Watchpoint Trigger)748
- ITM (Instrumentation Trace Macrocell)748
  - General Description748
  - Time Stamp Packets, Synchronization and Overflow Packets748
  - Table 139. Main ITM Registers749
- ETM (Embedded Trace Macrocell)750
  - General Description750
  - Signal Protocol, Packet Types750
  - Main ETM Registers750
  - Configuration Example751
- MCU Debug Component (DBGMCU)751
  - Debug Support for Low-Power Modes751
  - Table 140. Main ETM Registers751
  - Debug Support for Timers, Watchdog, and I C752
  - Debug MCU Configuration Register752
  - Debug MCU APB1 Freeze Register (DBGMCU_APB1_FZ)753
  - Debug MCU APB2 Freeze Register (DBGMCU_APB2_FZ)755
- TPIU (Trace Port Interface Unit)756
  - Introduction756
  - Figure 276. TPIU Block Diagram756
  - TRACE Pin Assignment757
  - Table 141. Asynchronous TRACE Pin Assignment757
  - Table 142. Synchronous TRACE Pin Assignment757
  - TPUI Formatter758
  - Table 143. Flexible TRACE Pin Assignment758
  - TPUI Frame Synchronization Packets759
  - Transmission of the Synchronization Frame Packet759
  - Synchronous Mode759
  - Asynchronous Mode760
  - TRACECLKIN Connection760
  - TPIU Registers760
  - Table 144. Important TPIU Registers760
  - 26.17.10 Example of Configuration761
- DBG Register Map762
- Table 145. DBG Register Map and Reset Values762
Device Electronic Signature763
- Unique Device ID Register (96 Bits)763
- Flash Size764
- Package Data Register764
Revision History765
- Table 146. Document Revision History765

Brand	ST
Model	STM32F410
Category	Microcontrollers
Language	English

ST STM32F410 User Manual

Table of Contents

Questions and Answers:

ST STM32F410 Specifications

Related product manuals