True random number generator (RNG) RM0401
260/771 RM0401 Rev 3
Section 13.4: RNG low-power usage.
• A sampling stage of these outputs clocked by a dedicated clock input (rng_clk),
delivering a 2-bit raw data output.
This noise source sampling is independent to the AHB interface clock frequency (rng_hclk).
Note: In Section 13.7: Entropy source validation recommended RNG clock frequencies are given.
Post processing
The sample values obtained from a true random noise source consist of 2-bit bitstrings.
Because this noise source output is biased, the RNG implements a post-processing
component that reduces that bias to a tolerable level.
The RNG post-processing consists of two stages, applied to each noise source bits:
• The RNG takes half of the bits from the sampled noise source, and half of the bits from
inverted sampled noise source. Thus, if the source generates more ‘1’ than ‘0’ (or the
opposite), it is filtered
• A linear feedback shift register (LFSR) performs a whitening process, producing 8-bit
strings.
This component is clocked by the RNG clock.
The times required between two random number generations, and between the RNG
initialization and availability of first sample are described in Section 13.6: RNG processing
time.
Output buffer
The RNG_DR data output register can store up to two 16-bit words which have been output
from the post-processing component (LFSR). In order to read back 32-bit random samples it
is required to wait 42 RNG clock cycles.
Whenever a random number is available through the RNG_DR register the DRDY flag
transitions from “0” to “1”. This flag remains high until output buffer becomes empty after
reading one word from the RNG_DR register.
Note: When interrupts are enabled an interrupt is generated when this data ready flag transitions
from “0” to “1”. Interrupt is then cleared automatically by the RNG as explained above.
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