Index–2
removal, 2–5
Control Output, 8–29
Control Relay Bit Map, 4–30
Converge Jump instruction, 7–23
Converge Stage instruction, 7–23
Convergence Stages, 7–19
Converting Number Formats
ASCII TO HEX, 5–86
Hex to ASCII, 5–87
Counter instruction, 5–36
Counter Instructions, 5–30
Counter Status Bit Map, 4–31
CPU
changing modes, 4–7
configuration, A–5
features, 4–2
hardware setup, 4–4
indicators, 9–6
instruction list, 5–2
Mode switch, 4–6
specifications, 4–3
status indicators, 4–6
CPU Indicator, 9–7
CPU Operation, 4–11
CPU Scan Time, 4–18
D
Data Label instruction, 5–106, 5–108
Decrement Binary instruction, 5–71
Derivative term, 8–34
Diagnostics, 9–2
Dimensions, 2–6
DIN rail mounting, 2–9
Direct-acting loop, 8–33
DirectNET, 4–35
Divide Double instruction, 5–70
Divide instruction, 5–69
DL05 Micro PLC
front panel, 2–4
mounting guidelines, 2–6
unit dimensions, 2–6
Drum instruction, 6–2, 6–12
chart representation, 6–3
counter assignments, 6–6
drum control techniques, 6–10
EDRUM (Event Drum), 6–14
handheld programmer mnemonics, 6–16
overview of drum operation, 6–8
powerup state, 6–9
self–resetting, 6–11
step transition, 6–4
Drum sequencer programming, 1–12
E
Emergency stop, 2–3
Enable Interrupt instruction, 5–104
Encode instruction, 5–77, 5–79, 5–81
End Instruction, 5–4
Environmental specifications, 2–8
Equal relays, 3–9, D–3, D–5
Error codes
code locations, 9–3
listing, B–2–B–9
pulse output errors, 3–43
Error term, 8–30
European Directives, F–2
Exclusive Or Double instruction, 5–60
Exclusive Or instruction, 5–59
Execution Times, C–3
F
Fatal Errors, 9–2
Fault instruction, 5–107
Feed forward control, 8–47
For instruction, 5–97
Fuse protection, 2–10
G
Goto Subroutine instruction, 5–99
Gray Code instruction, 5–89
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