Keysight U8903B - Page 472

A Appendixes
472 Keysight U8903B User’s Guide
DSI Config
Format
–Left
–Right
–I2S
–DSP
Select the data format
Fsync Polarity
– Rising
–Falling
This is only available when the format is Left or
Right.
Select the frame clock edge synchronization.
Fsync Wid th
– One Bit Clock
– One Subframe
– 50% Duty Cycle
This is only available when the format is Left or
Right.
Select the frame clock synchronization width.
Data Shift Cnt
This is only available when the format is Left or
Right.
Set the data shift count value.
Data Shift Dir
–Left
–Right
This is only available when the format is Left or
Right.
Select the data shift direction.
Word Length 8 to 32
Set the word length value. The word length value
must be greater than or equal to the audio
resolution.
Resolution 8 to 24 Set the audio resolution value.
Decoding
– Linear PCM
–A-Law
– μ-Law
Select the decoding format.
W/Bclk Dir
–In
–Out
Select the word/bit clock direction.
Bit Clk Edge
– Rising
–Falling
Select the bit clock edge.
Voltage
– 1.2 Vpp
– 1.5 Vpp
– 1.8 Vpp
– 2.5 Vpp
–3 Vpp
– 3.3 Vpp
– Custom
Select the input voltage value.
Table A-8 Digital analyzer menu tree description (continued)
Level 1 Level 2 Level 3 Level 4 Description