Renesas RL78/G10 - Page 235

RL78/G10 CHAPTER 6 TIMER ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 218
Dec 22, 2016
Figure 6-81. Example of Set Contents of Registers for Multiple PWM Output Function (Master Channel) (2/2)
(b) Timer output register 0 (TO0)
Bit 0
TO0
TO00
0
0: Outputs 0 from TO00.
(c) Timer output enable register 0 (TOE0)
Bit 0
TOE0
TOE00
0
0: Stops the TO00 output operation by counting operation.
(d) Timer output level register 0 (TOL0)
Bit 0
TOL0
TOL00
0
0: Setting is invalid because master channel output mode is set (TOM00 = 0).
(e) Timer output mode register 0 (TOM0)
Bit 0
TOM0
TOM00
0
0: Sets master channel output mode.