RL78/G10 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 378
Dec 22, 2016
Figure 12-77. Example of Contents of Registers for UART Reception (UART0 ) (2/2)
(e) Serial clock output register 0 (CKO0) … The register that not used in this mode.
(f) Serial output register 0 (SO0) … The register that not used in this mode.
(g) Serial output enable register 0 (SOE0) …The register that not used in this mode.
(h) Serial channel start register 0 (SS0) … Sets only the bits of the target channel is 1.
Caution For UART reception, be sure to set the SMR0r register of channel r that is to be paired with channel 0.
Remarks 1. n: Channel number (n = 1)
r: Channel number (r = n - 1) q: UART number (q = 0)
2. : Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
Symbol: 7 6 5 4 3 2 1 0
CKO0
0
0
0
0
0
0
CKO01
×
CKO00
×
Symbol: 7 6 5 4 3 2 1 0
SO0
0
0
0
0
0
0
SO01
×
SO00
×
Symbol: 7 6 5 4 3 2 1 0
SOE0
0
0
0
0
0
0
SOE01
×
SOE00
×
Symbol: 7 6 5 4 3 2 1 0
SS0
0
0
0
0
0
0
SS01
0/1
SS00
×
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