6.9.4 Operation as two-channel input with one-shot pulse output function ................................ 290
6.10 Cautions When Using Timer Array Unit ........................................................................................ 299
6.10.1 Cautions when using timer output ...................................................................................... 299
CHAPTER 7 12-BIT INTERVAL TIMER ...................................................................... 300
7.1 Functions of 12-bit Interval Timer ................................................................................................. 300
7.2 Configuration of 12-bit Interval Timer ........................................................................................... 300
7.3 Registers Controlling 12-bit Interval Timer ................................................................................... 301
7.3.1 Peripheral enable register 0 (PER0) .................................................................................. 301
7.3.2 Operation speed mode control register (OSMC) ............................................................... 302
7.3.3 Interval timer control register (ITMC) ................................................................................. 303
7.4 12-bit Interval Timer Operation ..................................................................................................... 304
7.4.1 12-bit interval timer operation timing .................................................................................. 304
7.4.2 Start of count operation and re-enter to HALT/STOP mode after returned from
HALT/STOP mode ............................................................................................................. 305
CHAPTER 8 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER ........................... 306
8.1 Functions of Clock Output/Buzzer Output Controller ................................................................... 306
8.2 Configuration of Clock Output/Buzzer Output Controller .............................................................. 307
8.3 Registers Controlling Clock Output/Buzzer Output Controller ...................................................... 307
8.3.1 Clock output select register 0 (CKS0) ................................................................................ 308
8.3.2 Registers controlling port functions of clock output/buzzer output pin ............................... 309
8.4 Operations of Clock Output/Buzzer Output Controller ................................................................. 310
8.4.1 Operation as output pin ...................................................................................................... 310
CHAPTER 9 WATCHDOG TIMER .............................................................................. 311
9.1 Functions of Watchdog Timer ....................................................................................................... 311
9.2 Configuration of Watchdog Timer ................................................................................................. 312
9.3 Register Controlling Watchdog Timer ........................................................................................... 313
9.3.1 Watchdog timer enable register (WDTE) ........................................................................... 313
9.4 Operation of Watchdog Timer ...................................................................................................... 314
9.4.1 Controlling operation of watchdog timer ............................................................................ 314
9.4.2 Setting time of watchdog timer ........................................................................................... 315
CHAPTER 10 A/D CONVERTER .................................................................................. 316
10.1 Function of A/D Converter ............................................................................................................ 316
10.2 Configuration of A/D Converter .................................................................................................... 318
10.3 Registers Controlling A/D Converter ............................................................................................ 320
10.3.1 Peripheral enable register 0 (PER0) .................................................................................. 321
10.3.2 A/D converter mode register 0 (ADM0) ............................................................................. 322
10.3.3 A/D converter mode register 2 (ADM2) ............................................................................. 326
10.3.4 10-bit A/D conversion result register (ADCR) .................................................................... 327
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