Renesas RL78/G15 - Peripheral Enable Register 0 (PER0)

RL78/G15 CHAPTER 11 COMPARATOR
R01UH0959EJ0110 Rev.1.10 Page 350 of 765
Mar 7, 2023
11.3.1 Peripheral Enable Register 0 (PER0)
This register enables or disables clock supply to each peripheral hardware macro. Clock supply to a hardware macro that
is not used is stopped in order to reduce the power consumption and noise.
When the comparator is used, be sure to set bit 6 (CMPEN) of this register to 1.
The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 11-2. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H After reset: 00H R/W
Symbol
□
7
□
6
□
5
□
4 3
□
2 1
□
0
PER0 TMKAEN CMPEN ADCEN IICA0EN 0 SAU0EN 0 TAU0EN
CMPEN Control of comparator input clock
0 Stops input clock supply.
●
SFR used by the comparator cannot be written.
●
The comparator is in the reset status.
1 Supplies input clock.
●
SFR used by the comparator can be read/written.
Caution When setting the comparator, be sure to set the CMPEN bit to 1 first before setting the registers
shown below. If CMPEN = 0, control registers of the comparator are cleared to their initial values and
writing to them is ignored (except for port mode registers 0 and 2 (PM0, PM2), port registers 0 and 2
(P0, P2), and port mode control registers 0 and 2 (PMC0, PMC2)).
 Comparator mode setting register (COMPMDR)
 Comparator filter control register (COMPFIR)
 Comparator output control register (COMPOCR)