Renesas RL78/G15

RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 381 of 765
Mar 7, 2023
12.3.6 Serial flag clear trigger register mn (SIRmn)
The SIRmn is a trigger register that is used to clear each error flag of channel n.
When each bit (FECTmn, PECTmn, OVCTmn) of this register is set to 1, the corresponding bit (FEFmn, PEFmn,
OVFmn) of serial status register mn is cleared to 0. Because the SIRmn is a trigger register, it is cleared immediately
when the corresponding bit of the SSRmn register is cleared.
The SIRmn register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SIRmn register can be set with an 8-bit memory manipulation instruction with SIRmnL.
The value of each SIRmn register is 0000H following a reset.
Figure 12-8. Format of Serial Flag Clear Trigger Register mn (SIRmn)
Address: F0108H, F0109H (SIR00) to F010AH, F010BH (SIR01) After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SIRmn 0 0 0 0 0 0 0 0 0 0 0 0 0
FECT
mn
Note 1
PECT
mn
OVCT
mn
FECT
mn
Note 1
Clear trigger of framing error flag of channel n
0 Not cleared
1 Clears the FEFmn bit of the SSRmn register to 0.
PECT
mn
Clear trigger of parity error flag of channel n
0 Not cleared
1 Clears the PEFmn bit of the SSRmn register to 0.
OVCT
mn
Clear trigger of overrun error flag of channel n
0 Not cleared
1 Clears the OVFmn bit of the SSRmn register to 0.
Note 1. The SIR01 register only.
Caution Be sure to clear bits 15 to 3 (or bits 15 to 2 for the SIR00 register) to 0
Remark 1. m: Unit number (m = 0), n: Channel number (n = 0, 1)
Remark 2. When the SIRmn register is read, 0000H is always read.