Renesas RL78/G15 User Manual

RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 373 of 765
Mar 7, 2023
12.3.2 Serial clock select register m (SPSm)
The SPSm is a 16-bit register that is used to select two types of operation clocks (CKm0, CKm1) that are commonly
supplied to each channel. CKm1 is selected by bits 7 to 4 of the SPSm register, and CKm0 is selected by bits 3 to 0.
Rewriting the SPSm register is prohibited when the register is in operation (when SEmn = 1).
The SPSm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SPSm register can be set with an 8-bit memory manipulation instruction with SPSmL.
The value of each SPSm register is 0000H following a reset.
Figure 12-4. Format of Serial Clock Select Register m (SPSm)
Address: F0126H, F0127H (SPS0) After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPSm 0 0 0 0 0 0 0 0
PRSm
13
PRSm
12
PRSm
11
PRSm
10
PRSm
03
PRSm
02
PRSm
01
PRSm
00
PRSmk3 PRSmk2 PRSmk1 PRSmk0 Selection of operation clock (CKmk)
Note 1
f
CLK
(MHz)
1 2 4 8 16
0 0 0 0 f
CLK
1 MHz 2 MHz 4 MHz 8 MHz 16 MHz
0 0 0 1 f
CLK
/2 500 kHz 1 MHz 2 MHz 4 MHz 8 MHz
0 0 1 0 f
CLK
/2
2
250 kHz 500 kHz 1 MHz 2 MHz 4 MHz
0 0 1 1 f
CLK
/2
3
125 kHz 250 kHz 500 MHz 1 MHz 2 MHz
0 1 0 0 f
CLK
/2
4
62.5 kHz 125 kHz 250 kHz 500 kHz 1 MHz
0 1 0 1 f
CLK
/2
5
31.25 kHz 62.5 kHz 125 kHz 250 kHz 500 kHz
0 1 1 0 f
CLK
/2
6
15.63 kHz 31.25 kHz 62.5 kHz 125 kHz 250 kHz
0 1 1 1 f
CLK
/2
7
7.81 kHz 15.63 kHz 31.25 kHz 62.5 kHz 125 kHz
1 0 0 0 f
CLK
/2
8
3.91 kHz 7.81 kHz 15.63 kHz 31.25 kHz 62.5 kHz
1 0 0 1 f
CLK
/2
9
1.95 kHz 3.91 kHz 7.81 kHz 15.63 kHz 31.25 kHz
1 0 1 0 f
CLK
/2
10
977 Hz 1.95 kHz 3.91 kHz 7.81 kHz 15.63 kHz
1 0 1 1 f
CLK
/2
11
488 Hz 977 Hz 1.95 kHz 3.91 kHz 7.81 kHz
1 1 0 0 f
CLK
/2
12
244 Hz 488 Hz 977 Hz 1.95 kHz 3.91 kHz
1 1 0 1 f
CLK
/2
13
122 Hz 244 Hz 488 Hz 977 Hz 1.95 kHz
1 1 1 0 f
CLK
/2
14
61 Hz 122 Hz 244 Hz 488 Hz 977 Hz
1 1 1 1 f
CLK
/2
15
31 Hz 61 Hz 122 Hz 244 Hz 488 Hz
Note 1. When changing the clock selected for f
CLK
(by changing the system clock control register (CKC) value), do so
after having stopped (serial channel stop register m (STm) = 000FH) the operation of the serial array unit
(SAU).
Caution Be sure to clear bits 15 to 8 to 0.
Remark 1. f
CLK
: CPU/peripheral hardware clock frequency
Remark 2. m: Unit number (m = 0)
Remark 3. k: Channel number (k = 0, 1)

Renesas RL78/G15 Specifications

General

Brand	Renesas
Model	RL78/G15
Category	Microcontrollers
Language	English