RL78/G15 CHAPTER 6 TIMER ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 199 of 765
Mar 7, 2023
6.3.13 Noise filter enable registers 1 (NFEN1)
The NFEN1 register is used to set whether the noise filter can be used for the timer input signal to each channel.
Enable the noise filter by setting the corresponding bits to 1 on the pins in need of noise removal.
When the noise filter is enabled, after synchronization with the operation clock (f
MCK
) for the target channel, whether the
signal keeps the same value for two clock cycles is detected. When the noise filter is disabled, the input signal is only
synchronized with the operation clock (f
MCK
) for the target channel
Note 1
.
The NFEN1 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Note 1. For details, see 6.5.1(2) When valid edge of input signal via the TImn pin is selected (CCSmn = 1), 6.5.2
Start timing of counter, and 6.7 Timer Input (TImn) Control.
Figure 6-21. Format of Noise Filter Enable Registers 1 (NFEN1) (1/2)
Address: F0071H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
NFEN1 TNFEN07 TNFEN06 TNFEN05 TNFEN04 TNFEN03 TNFEN02 TNFEN01 TNFEN00
TNFEN07 Enable/disable using noise filter of TI07 pin
0 Noise filter OFF
1 Noise filter ON
TNFEN06 Enable/disable using noise filter of TI06 pin
0 Noise filter OFF
1 Noise filter ON
TNFEN05 Enable/disable using noise filter of TI05 pin
0 Noise filter OFF
1 Noise filter ON
TNFEN04 Enable/disable using noise filter of TI04 pin
0 Noise filter OFF
1 Noise filter ON
TNFEN03 Enable/disable using noise filter of TI03 pin
0 Noise filter OFF
1 Noise filter ON
Remark The presence or absence of timer I/O pins of channel 0 to 7 depends on the product. See Table 6-2 Timer
I/O Pins provided in Each Product.
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