RL78/G15 CHAPTER 3 CPU ARCHITECTURE
R01UH0959EJ0110 Rev.1.10 Page 73 of 765
Mar 7, 2023
3.3.5 Extended special function registers (2nd SFRs: 2nd Special Function
Registers)
Unlike a general-purpose register, each extended SFR (2nd SFR) has a special function.
Extended SFRs are allocated to the F0000H to F07FFH area. SFRs other than those in the SFR area (FFF00H to
FFFFFH) are allocated to this area. An instruction that accesses the extended SFR area, however, is 1 byte longer than
an instruction that accesses the SFR area.
Extended SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation
instructions. The manipulable bit units, 1, 8, and 16, depend on the extended SFR type.
Each manipulation bit unit can be specified as follows.
[1-bit manipulation]
Describe as follows for the 1-bit manipulation instruction operand (!addr16.bit).
When the bit name is defined: <Bit name>
When the bit name i
s not defined: <
Register name>.
<Bit number
> or <Addres
s>.<Bit num
ber>
[8-bit manipulation]
Describe the symbol defined by the assembler for the 8-bit manipulation instruction operand (!addr16). This manipulation
can also be specified with an address.
[16-bit manipulation]
Describe the symbol defined by the assembler for the 16-bit manipulation instruction operand (!addr16). When specifying
an address, describe an even address.
Table 3-6 gives a list of the extended SFRs. The meanings of items in the table are as follows.
[Symbol]
Symbol indicating the address of an extended SFR. It is a reserved word in the assembler, and is defined as an sfr
variable using the #pragma sfr directive in the compiler. When using the assembler, debugger, and simulator, symbols
can be written as an instruction operand.
[R/W]
Indicates whether the corresponding extended SFR can be read or written.
R/W: Read/write enable
R: Read only
W: Write only
[Manipulable bit units]
“” indicates the manipulable bit unit (1, 8, or 16). “—” indicates a bit unit for which manipulation is not possible.
[After reset]
Indicates each register status upon reset signal generation.
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