RL78/G15 CHAPTER 6 TIMER ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 245 of 765
Mar 7, 2023
6.8.4 Operation as input pulse interval measurement
The count value can be captured on detection of a valid edge of TImn pin input and the interval of the pulse input to TImn
pin can be measured. In addition, the count value can be captured by setting TSmn to 1 by software during the period of
TEmn = 1.
For the UART0 baud rate correction, set bit 1 (ISC1) of the input switch control register (ISC) to 1.
In the following descriptions, read TI0n as RXD0. When the ISC1 bit is set to 1, the input signal of the serial data input
(RXD0) pin is selected as a timer input (TI01). The width at the baud rate (transfer rate) of the other party in
communications can be measured by using the input pulse interval measurement mode with the input edge signal of the
start bit as a trigger.
The input pulse interval can be calculated by the following expression.
TImn input pulse interval = Period of count clock × ((10000H × TSRmn: OVF) + (Capture value of TDRmn + 1))
Caution The TImn pin input is sampled using the operation clock selected with the CKSmn bit of timer mode
register mn (TMRmn), so an error of one cycle of the operation clock occurs.
Timer count register mn (TCRmn) operates as an up counter in the capture mode.
When the channel start trigger bit (TSmn) of timer channel start register m (TSm) is set to 1, the TCRmn register counts
up from 0000H in synchronization with the count clock.
When the TImn pin input valid edge is detected, the count value of the TCRmn register is transferred (captured) to timer
data register mn (TDRmn) and, at the same time, the TCRmn register is cleared to 0000H, and the INTTMmn is output. If
the counter overflows at this time, the OVF bit of timer status register mn (TSRmn) is set to 1. If the counter does not
overflow, the OVF bit is cleared. After that, the above operation is repeated.
As soon as the count value has been captured to the TDRmn register, the OVF bit of the TSRmn register is updated
depending on whether the counter overflows during the measurement period. Therefore, the overflow status of the
captured value can be checked.
If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF bit of
the TSRmn register is set to 1. However, a normal interval value cannot be measured for the OVF bit, if two or more
overflows occur.
Set the STSmn2 to STSmn0 bits of the TMRmn register to 001B to use the valid edges of TImn as a start trigger and a
capture trigger.
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