RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0959EJ0110 Rev.1.10 Page 585 of 765
Mar 7, 2023
13.6 Timing Charts
In the I
2
C bus mode, the master outputs an address on the serial bus to select a target slave device from among several
slave devices.
The master transmits the TRC0 bit (bit 3 of IICA status register 0 (IICS0)) that indicates the data transfer direction
following the slave address and starts serial communication with the slave.
Figure 13-31 and Figure 13-32 show timing charts of data communication.
Shift operation of IICA shift register 0 (IICA0) proceeds in synchronization with the falling edge of the serial clock
(SCLA0), and the transmit data is transferred to the SO latch and output from the SDAA0 pin with the MSB first.
The data input to the SDAA0 pin is captured in IICA0 at the rising edge of SCLA0.
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