RL78/G15 CHAPTER 10 A/D CONVERTER
R01UH0959EJ0110 Rev.1.10 Page 342 of 765
Mar 7, 2023
10.9 Notes on A/D Converter
10.9.1 Operating current in STOP mode
Shift to STOP mode after stopping the A/D converter (by setting bit 7 (ADCS) of A/D converter mode register 0 (ADM0)
to 0). The operating current can be reduced by setting bit 0 (ADCE) of the ADM0 register to 0 at the same time.
10.9.2 Input voltage on ANI0 to ANI10 pins
Observe the rated range of the ANI0 to ANI10 pins input voltage. If a voltage exceeding V
DD
or a voltage lower than V
SS
(even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel
becomes undefined. In addition, the converted values of the other channels may also be affected.
10.9.3 Conflicting operations
(1) If writing to the A/D conversion result register (ADCR, ADCRH) at the end of conversion and reading of the ADCR
or ADCRH register by software operation are in contention, the latter is given priority.
After the read operation, the new conversion result is written to the ADCR or ADCRH register.
(2) If writing to the ADCR or ADCRH register at the end of conversion and writing to A/D converter mode register 0
(ADM0) are in contention, the latter is given priority. Writing to the ADCR or ADCRH register is not performed, nor
is the A/D conversion end interrupt signal (INTAD) generated.
10.9.4 Noise countermeasures
To maintain the 10-bit resolution, attention must be paid to noise on V
DD
and the ANI0 to ANI10 pins.
(1) Connect a capacitor with a low equivalent resistance and a good frequency response to the power supply.
(2) The higher the output impedance of the analog input source, the greater the influence. To reduce noise, we
recommend connecting C externally as shown in Figure 10-22.
(3) Do not switch other pins during conversion.
(4) The accuracy is improved if the HALT mode is set immediately after the start of conversion.
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