Renesas RL78/G15

RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0959EJ0110 Rev.1.10 Page 513 of 765
Mar 7, 2023
13.3.1 Peripheral enable register 0 (PER0)
The PER0 register is used to enable or disable the supply of a clock signal to various on-chip peripheral modules. Clock
supply to an on-chip peripheral module that is not to be used can be stopped to decrease power consumption and noise.
When serial interface IICA is used, be sure to set bit 4 (IICA0EN) to 1.
The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 13-5. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H After reset: 00H R/W
Symbol
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7
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6
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5
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4 3
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2 1
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0
PER0 TMKAEN CMPEN ADCEN IICA0EN 0 SAU0EN 0 TAU0EN
IICA0EN Control of serial interface IICA input clock supply
0 Stops supply of an input clock.
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The SFRs used by serial interface IICA cannot be written.
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Serial interface IICA is in the reset state.
1 Enables supply of an input clock.
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The SFRs used by serial interface IICA can be read/written.
Caution 1. When setting serial interface IICA, make sure that the setting of the IICA0EN bit is 1 before setting
the following registers. If IICA0EN = 0, the values of the registers which control the serial interface
IICA are cleared to their initial values, and writing to them is ignored (except for port mode register
0 (PM0), port register 0 (P0), port output mode register 0 (POM0), and port mode control register 0
(PMC0)).
 IICA control register 00 (IICCTL00)
 IICA flag register 0 (IICF0)
 IICA status register 0 (IICS0)
 IICA control register 01 (IICCTL01)
 IICA low-level width setting register 0 (IICWL0)
 IICA high-level width setting register 0 (IICWH0)
Caution 2. Be sure to clear bits 1 and 3 to 0.