RL78/G15 CHAPTER 7 12-BIT INTERVAL TIMER
R01UH0959EJ0110 Rev.1.10 Page 301 of 765
Mar 7, 2023
7.3 Registers Controlling 12-bit Interval Timer
The 12-bit interval timer is controlled by the following registers.
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Peripheral enable register 0 (PER0)
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Operation speed mode control register (OSMC)
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Interval timer control register (ITMC)
7.3.1 Peripheral enable register 0 (PER0)
This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the hardware
that is not used is also stopped so as to decrease the power consumption and noise.
When using the 12-bit interval timer, be sure to set bit 7 (TMKAEN) to 1 at first.
The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 7-2. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H After reset: 00H R/W
Symbol
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7
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6
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5
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4 3
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2 1
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0
PER0 TMKAEN CMPEN ADCEN IICA0EN 0 SAU0EN 0 TAU0EN
TMKAEN Control of 12-bit interval timer input clock supply
0 Stops input clock supply.
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SFR used by the 12-bit interval timer cannot be written.
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The 12-bit interval timer is in the reset status.
1 Enables input clock supply.
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SFR used by the 12-bit interval timer can be read and written.
Caution 1. Set the WUTMMCK0 bit of the OSMC register to 1 to determine the clock source for counting before
supplying an input clock signal to the 12-bit interval timer (TMKAEN = 1).
Caution 2. When setting the 12-bit interval timer, be sure to first set the TMKAEN bit to 1 and then set the
following register, while oscillation of the count clock is stable.
If TMKAEN = 0, writing to the 12-bit interval timer is ignored, and all read values are default values
(except for the operation speed mode control register (OSMC)).
Interval timer control register (ITMC)
Caution 3. Be sure to clear bits 1 and 3 to 0.
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